Hybrid analytical modeling of noise coupling to signal traces in a power bus with embedded film capacitor

An accurate hybrid analytical method is proposed to determine the coupling of switching noise to signal traces in a multilayer power bus with embedded film capacitor. We used the induction equivalent theorem to derive the solution of noise coupling and the segmentation method to calculate the electric field of the noise in a power bus. The proposed method was verified by measurements of impedance parameters in the frequency domain.     

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach.     

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.     

HE331型、HE341型、HE351型、微型超高频宽带混合集成放大电路

本文介绍了一种国际通用管壳封装的超小型混合集成放大电路。该电路采用薄膜混合集成技术,将微波管芯、薄膜电阻、平面螺旋电感等集成于一个φ8.4mm的B-3金属管壳之中。采用了负反馈加电抗补偿等集总参数设计,并提供了一种典型负反馈宽带低噪声放大器的简化计算方法。设计了一种用超声键合法在微型管壳内动态调试放大器的技术方法。     

A Packaging Solution for Optically Testing Wire-Bonded Chips

In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal–oxide–semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.      

Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

The use of deep-submicrometer (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of a chip. In this paper, we present a technique that reduces crosstalk noise on instruction buses. While previous research focuses primarily on address buses, little work can be applied efficiently to instruction buses. This is due to the complex transition behavior of instruction streams. Based on instruction sequence profiling, we exploit an architecture that encodes pairs of bus wires and permute them in order to optimize power and noise. A close to optimal architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 50.79% and power consumption up to 55% on instruction buses.     

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz.      

Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method

In this paper, a multilayered on-chip power distribution network consisting of two million passive elements has been modeled using the finite-difference time-domain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately.     

基于耦合边界的紧凑型光子晶体 定向耦合器的优化设计

本文采用平面波展开法分析了双线型缺陷并列平行光子晶体波导的带隙结构、缺陷模式及耦合长度,提出了一种具有耦合边界的光子晶体定向耦合器,并探讨了光波在其中的传输性能.同时基于平面波展开法及时域有限差分法,深入分析和讨论了光波在光子晶体并列波导、光子晶体直角转弯模块中的工作模式和传输特性.利用该光子晶体定向耦合器结合光子晶体转角器件可以将两根平行标准单模光纤传输模式组合成交叉态、直通态和功分态等状态.仿真结果表明在交叉态和直通态时,使用该光子晶体定向耦合器的传输峰值可以在较大频率带宽内达到90%以上.     

Autonomous adaptive frequency assignment for TDMA portable radiosystems

A simple autonomous procedure performed by each radio port (base station) to determine its own transmitting frequency is proposed. This procedure consists of signal strength measurements and an algorithm which selects the frequency with minimum interference from other ports. The algorithm converges rapidly while adapting to changes of operational conditions, such as installing new ports, which changes the system configuration, or adding new buildings, which causes different shadow fading. This method is significantly superior to a random assignment method both in resultant channel quality and in traffic-handling capability. For a regular-grid configuration, this method performs nearly as well as an a priori optimal frequency assignment method. It is also found that this assignment algorithm is robust against short-term signal fluctuations and it can be performed completely autonomously by each radio port     

Modeling of irregular shaped power distribution planes usingtransmission matrix method

A major problem in power distribution networks is simultaneous switching noise (SSN), which causes several signal integrity issues. To understand the behavior of the power distribution system (PDS) and its contribution to SSN, noise prediction methods are necessary. This paper presents a method for analyzing arbitrary shaped power distribution networks both in the frequency and time domain. Using a two dimensional array of distributed RLCG circuits, the impedance of a power/ground plane pair is computed. For the efficient computation of the power distribution impedances at specific points in the network, a multi-input and multi-output transmission matrix method has been used. To verify the accuracy of this method, the simulation results have been compared with Spice which uses a circuit based approach and an analytical solution based on the cavity modes in the structure. The simulation results have also been compared with measurements for an L-shaped structure. The transmission matrix method has been applied to a split plane and an arbitrary shaped power plane to demonstrate the application of this technique to irregular geometries     

Multiple twisted dataline techniques for multigigabit DRAMs

To provide reliable scaled DRAMs, new multiple twisted dataline techniques are proposed and analyzed. Their effectiveness in reducing both the bitline (BL) and wordline (WL) coupling noises in scaled DRAM's was evaluated by means of soft-error-rate measurements on 256-Mbit and 1-Gbit DRAM test chips. At the 1-Gbit level of integration, in our proposed scheme-compared to the conventional twisted bitline (TBL) scheme-the chip area penalty due to twisting is reduced by 66% and the BL coupling noise is reduced by 45%. At the 256-Mbit level, when the proposed technique is applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional TBL and WL schemes. Faster data access time can also be expected when the proposed technique is applied to BL and/or WL structures     

Estimating the noise mitigation effect of local decoupling in printed circuit boards

Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bits noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling.     

The latch bus driver system

A large and growing fraction of the power in modern VSLI chips is dissipated by the drivers of external bus lines. A novel bus system drastically reduces power and noise by using a central driver chip which periodically attempts to charge and to discharge the bus lines. The transmitters of the selected chip inhibit the charge process for the establishment of a `low' signal. The central driver latches the signal state after the inhibit phase. The authors explain the inhibit driver principle in comparison with the usual push-pull system, present the timing characteristics, and report on the design and the measured results of an experimental central driver chip in full-custom CMOS     

Circuit models for power bus structures on printed circuit boards using a hybrid FEM-SPICE method

Power bus structures consisting of two parallel conducting planes are widely used on high-speed printed circuit boards. In this paper, a full-wave finite-element method (FEM) method is used to analyze power bus structures, and the resulting matrix equations are converted to equivalent circuits that can be analyzed using SPICE programs. Using this method of combining FEM and SPICE, power bus structures of arbitrary shape can be modeled efficiently both in the time-domain and frequency-domain, along with the circuit components connected to the bus. Dielectric loss and losses due to the finite resistance of the power planes can also be modeled. Practical examples are presented to validate this method.     

45nm体硅工艺下使用双-栅氧化层厚度降低SRAM的泄漏功耗

提出了一种在45nm体硅工艺下使用双-栅氧化层厚度来降低整体泄漏功耗的方法.所提方法具有不增加面积和延时、改善静态噪声边界、对SRAM设计流程的改动很小等优点.提出了三种新型的SRAM单元结构,并且使用这些单元设计了一个32kb的SRAM,仿真结果表明,整体泄漏功耗可以降低50%以上.     

A technique for elimination of reflected rays from antenna measurements performed in echoic environment

The paper describes a technique for analyzing antenna measurements and removing reflected components present in measurements performed in echoic environments. The method is based on digital signal processing methods, and frequency-domain measurements are used to design a discrete-time, finite impulse response digital filter using least-squares methods. The frequency response of the filter is equal to the transmission coefficient measurements performed in an anechoic chamber. In order to verify the method, processed measurements of mutual coupling between stacked patch antennas were compared to the computer simulations of anechoic response, and a very close agreement was achieved.     

一种I2C总线快速收发器设计

I2C总线是飞利浦公司在1992年推出的芯片间互连的双向串行总线标准,与传统的并行连接相比,他具有只需要2根连接线,使用统一的串行协议来实现寻址与数据传递。I2C总线收发器的难点主要在于低噪声、低功耗和标准兼容性,本文描述了I2C总线收发器的设计,包括电路设计、版图设计以及模拟结果。Spice仿真结果表明该总线收发器达到了I2C标准要求。     

Design and Validation of a Power Supply Noise Reduction Technique

For the high-performance microprocessors with high-bandwidth I/O, the power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high-quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). In this paper, we will present two implementations of an approach of using on-die resistors in series with the package capacitance to dampen the high-frequency noise. We will show by validation on the 90-nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings. The results of several validation experiments, including the measurement of noise and impedance of the I/O power delivery, and the post-layout simulation will also be presented.