WCDMA功放预失真发生器的研究

针对宽带码分多址(WCDMA)功放的非线性失真问题,提出了一种简单有效的解决方案,即通过预失真发生器对幅度-幅度(AM-AM)及幅度-相位(AM-PM)曲线进行调整,以补偿功放的非线性失真.这种方案主要是通过利用二极管的非线性特性设计出的预失真发生器来实现的.实验证明,将预失真发生器与WCDMA功放配合使用,能将功放的邻道功率泄漏比(ACPR)改善5 dB.     

宽带系统中有记忆大功率功放的数字预失真器研究

针对高峰均比的宽带输入信号,提出了一套联合峰均比抑制技术和基带自适应预失真技术的数字预失真器设计方案,并仿真了峰值抵消算法和自适应预失真算法.结果表明对于峰均比为8.4 dB的输入信号,经过1.5 dB的削峰处理后,预失真器改善带外频谱抑制27 dB,非常有效地补偿了功放的非线性失真,提高了功放效率,对发射机功放线性化技术有一定的实用价值.     

用于5G RF PA 线性化的多频段通用数字预失真器

文中提出了一种基于独热编码与长短时期记忆 (LSTM) 神经网络的多频段通用数字预失真非线性 模型,它可以有效地对工作在多个频段的宽带射频功放进行线性化。在训练集中引入表示不同频率信号的不同独 热编码,训练后的神经网络非线性模型可以在不改变网络结构和模型参数的情况下对不同频段的功率放大器进行 预失真线性化。为了验证该方法的有效性,建立了两个分别工作于2. 6 GHz 和4. 9 GHz 的射频功放实验平台,在这 两个频段预失真非线性建模的归一化均方误差(NMSE)均可达到-40 dB,然后使用100 MHz 带宽5G NR 信号,分别 对这两个射频功放进行预失真线性化实验验证。实验结果表明,该多频段通用数字预失真器可以将这两个功放的 邻信道泄漏比(ACLR)在中心频率下偏100 MHz 处分别改善19. 42 dB 和17. 91 dB,在中心频率上偏100 MHz 处分 别改善15. 73 dB 和15. 17 dB,验证了所提非线性模型的有效性。     

基于DSP和FPGA的短波功放数字预失真算法实现

介绍了宽带跳频短波电台中功率放大器的线性化技术。针对短波通信中功率放大器的多载波宽带信号失真特性,提出基于二维复数增益补偿的查找表模型数字预失真线性化方案,并且通过TI公司的DSP(TMS320C6455)与Altera公司的FPGA(Cyclone EP4CGX150CF2317)混合平台实现短波功放数字预失真算法及整个环路的实时自适应系统。实验结果表明该方案改善短波功放输出信号的邻道功率比(ACPR)达25dB以上,有效补偿了短波功放的非线性失真,大幅度提高了短波电台的通信质量。     

一种基于延迟线补偿记忆效应的模拟预失真器

模拟预失真器具有带宽宽、结构简单、功耗低和延时少等优点,满足第五代移动通信系统(5G)及超 5G 的功放线性化对大带宽、低功耗和低延时的要求。然而随着移动通信系统的发展,信号的带宽和调制度越来越 高,功率放大器的记忆效应影响也越来越强,而传统的模拟预失真器无法补偿功放的记忆效应。为了解决模拟预失 真电路的记忆效应补偿问题,文中提出了一种基于延迟线补偿记忆效应的肖特基二极管模拟预失真器(SDD-APD)。 该模拟预失真器采用不等长微带线作为延迟线,用来补偿功放的记忆效应。采用100 MHz 带宽5G 新无线电(NR) 信号对工作在3. 5 GHz 的AB 类功放进行测试,结果表明该模拟预失真器可以补偿功放的记忆效应,并能将功放的 非线性改善10 dB 以上。     

射频模拟预失真器的研究与设计

利用小信号BJT放大器的非线性特性设计了一个有源模拟预失真器.通过调整小信号放大器的偏置状态和对失真信号的提取控制,使功放的三阶互调失真得到了明显的改善.双音实测数据表明,该预失真器使一个GSM基站功放在5 dB功率回退点附近的三阶互调失真改善了18 dB左右,与传统的射频预失真器相比,该预失真器对功放三阶互调失真的改善度提高了10 dB左右.     

一种基于记忆多项式射频功放的直接MP模型预失真方案

针对短波射频功放的非线性失真及记忆效应失真问题,提出了一种直接学习结构的MP模型预失真方案,采用Filtered-X LMS(NFXLMS)算法对建立的预失真模型进行训练辨识。仿真分析,针对MP模型高功率放大器,预失真后的三阶互调分量改善了52.2dB,五阶互调分量改善了48.85dB,与现有的IIR Wiener预失真器相比较,进一步提高了功放输出的线性度。同时,在DSP+FPGA平台上对MP模型预失真算法进行实测,结果表明,该预失真器能有效改善实际功放的非线性失真,具有较好的线性化效果。     

WCDMA系统中基于查找表的预失真技术的研究

在无线通信系统中,高功率放大器因其非线性,导致AM/PM效应使得微分相位、微分增益和互调失真变坏.高质量的通信系统设计应尽可能减小功率放大器的AM/PM效应.因此,针对宽带码分多址(WCDMA)功放的非线性失真问题,采用一种基于查找表(LUT)的自适应预失真方法,改善功放的非线性失真.仿真表明, 该方法能有效补偿放大器产生的AM-AM、AM-PM失真,并将功放的邻道功率泄漏比(ACPR)改善到30 dB左右.     

一种新的混合预失真器的设计

通信技术的发展对于功率放大器的要求越来越高,主要集中在高线性、高效率的功放.预失真是目前改善功放线性比较好的方法.新的自适应混合预失真系统充分利用模拟预失真,快速简单的和数字预失真算法的精确,输入信号先后经过模拟、数字两级预失真系统,并结合信号包络检测技术进行带外信号调节.通过对仿真结果的比较,IMD性能比单独使用数字预失真系统有了8 dB的改善,同时收敛时间也有所减少.     

毫米波功率放大器的预失真线性化改进研究

针对毫米波功率放大器的非线性失真问题,提出一种记忆多项式预失真优化算法,对功放的非线性失真进行补偿。预失真处理前后功放特性曲线表明该预失真算法的线性化效果明显;预失真处理后输出信号的相邻信道功率比原始输入信号高0.89 dB,比预失真前降低了7.8 dB,降低了相邻信道的干扰,符合理想功放线性化放大原则。     

A modified class-F power amplifier with miniaturized harmonic control circuit

In this paper, a modified class-F power-amplifier (PA) for GSM applications is designed, simulated and tested. In this design, novel symmetrical meandered lines compact microstrip resonant cell (SMLCMRC), is proposed as a new harmonics control circuit (HCC), which resulted in size compression, power added efficiency (PAE) enhancement, power gain improvement, and better linearization in the PA. In this work both of the conventional class-F amplifier and proposed amplifier with SMLCMRC is designed at 1.8 GHz. The measurements show that the proposed PA with SMLCMRC has 72.54% maximum PAE, 17.13 dB gain and the 1 dB compression point (P1dB) is about 35.1 dBm. These results show, 16.5% improvement in PAE, 1.33 dB increment in gain and 1.1 dB improvement in linearity operating range of proposed amplifier compared to the conventional PA.     

简洁构型与馈电的宽带双极化金属锥阵列天线北大核心CSCD

本文提出了一种宽带双极化金属锥阵列天线。该阵列天线以传统的旋转体天线结构为主体,通过在锥体底部开设四道正交的直通槽,以便在锥状单元内部形成可与地板间构成匹配谐振腔的开放式空腔结构。在阵列中,任意两个相邻的锥状单元之间可形成类似于Vivaldi天线的辐射缝隙结构。馈电采用同轴馈电方式,探针无弯折结构,金属锥体无弯折过孔。每个金属锥状单元独立,可极大简化加工、装配和维护过程。该天线具有两个正交极化,分别由左右和前后相邻单元构成。仿真结果表明,在频率范围为2～8GHz内,阵列大部分有源VSWR小于2,小部分端口有源VSWR小于2.5 (相对带宽为120%)。     

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.     

A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications

This paper demonstrates a two-stage 1.95-GHz WCDMA handset RFIC power amplifier (PA) implemented in a 0.25-/spl mu/m SiGe BiCMOS process. With an integrated dual dynamic bias control of the collector current and collector voltage, the average power efficiency of the two-stage PA is improved from 1.9% to 5.0%. The measured power gain is 18.5 dB. The gain variation with dynamic biasing is less than 1.8 dB. An off-chip memoryless digital predistortion linearizer is also adopted, satisfying the 3GPP wideband code division multiple access (WCDMA) linearity specification by a 10 dB improvement of adjacent channel power ratio (ACPR) at +26 dBm average channel output power.     

Reduction of Crosstalk Between Dual Power Amplifiers Using Laser Treatment

A cost-effective isolation technique using laser treatment is proposed to suppress the undesired crosstalk between dual power amplifiers (PAs), which are essential to multiple-input multiple-output communications system. Laser treatment not only reduces the small-signal coupling between dual PAs but also enhances the linearity of the PA under dual-PA operation mode. The figure of merit for the small-signal coupling has an improvement of 4.55 dB at 2.45 GHz, and the output power at 3% (${-}$ 30 dB) error vector magnitude (EVM) has a linearity improvement of 6.1 dB under 0-dB interference.      

A predistortion linearizer using a tunable resonator

In this letter, a novel predistortion topology using a tunable resonator is presented. The core of the circuit is a series tunable resonator employing a reverse biased varactor diode. The junction capacitance of the varactor diode increases with RF input power, effectively shifting the resonant frequency of the circuit. This results in the amplitude and phase deviations at the frequency of operation. A 1.8-GHz power amplifier (PA), with a gain of 9 dB and 21-dBm output power, is linearized based on this technique. A maximum of 11 dB improvement in adjacent channel power ratio and an increase in 1.8 dB for the compression point is measured for the linearized PA.     

Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12×1.25 mm2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85℃ converges within±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.