共查询到20条相似文献,搜索用时 62 毫秒
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可编程增益放大器(PGA)主要应用于无线传感网络射频前端接收机芯片.PGA的设计采用0.18 μm RF CMOS工艺,以负载可编程为基础实现增益可变.PGA电压增益范围1~60 dB,增益步长1 dB,增益误差小于0.5 dB,中心频率为2MHz,3 dB带宽大于3.2 MHz.通过控制放大器尾电流源工作与否来实现功耗管理.当电源电压为1.8 V时,最大功耗为4mw,最小功耗为1.3 mW.通过仿真验证,PGA性能能够满足系统设计要求. 相似文献
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采用标准0.18μm CMOS工艺,设计了一种应用于超高频射频识别(UHF RFID)发射机的高精度可编程增益放大器(PGA).该PGA由增益细调级和增益粗调级级联形成.增益细调级采用闭环电阻反馈技术,实现了增益的精确控制,并提高了线性度.增益粗调级采用开环源极负反馈技术,实现了增益的粗略控制,并降低了功耗.仿真结果表明,在1.8V工作电压下,整个可编程增益放大器的功耗为2.69mW,增益动态范围为-12~24dB,步长为1dB,增益误差0.02dB;-12dB增益下输入1dB压缩点为-5.54dBm. 相似文献
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这篇文章呈现了一个应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器,使用了改进的带负电容抵消技术Cherry-hooper放大器作为增益单元,采用了新颖的电路技术来实现增益调节,该技术在宽带PGA的设计中具有普适性,并且可以大大简化宽带PGA的设计。PGA通过两级增益单元和一级输出BUFFER的级联获得了最大增益30dB和远宽于3GHz的带宽。该PGA集成进整个60GHz无线收发机里面并且用TSMC65nm的CMOS工艺获得实现。整个接收机前端的测试结果表明接收机前端获得了18dB的可变增益范围和>3GHz的带宽,这证明提出的PGA本身获得了18dB的可变增益范围并且带宽是远大于3GHz的。该PGA电源电压为1.2V,功耗为10.7mW,核心版图面积仅仅为0.025mm^2。 相似文献
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《Spectrum, IEEE》1994,31(7):15
Bits are among the most anonymous, most elusive entities in the universe. Bits weigh nothing, occupy no space, obey no physical law, can be created spontaneously from nothingness, and can be endlessly replicated. Each in itself is the merest quantum of the Information Age, yet taken together all those little 1s and 0s are acting as if they were the most important force on the planet. And if you want indestructibility, then a bit is forever. The author briefly discusses the role of the bit in today's society 相似文献
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大部分传统的位同步器是针对固定位速率遥测系统来设计的,这不能满足一些可变位速率遥测接收机的需求。因此,提出一种基于FPGA实现的位同步器的设计,它能适应不同位速率的遥测系统。同时,对这种位同步器的实现进行了仿真,验证其正确性和可实现性。 相似文献
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An optimal bit rate conversion scheme for MPEG-2 video bit streams, based on a drift free video transcoder, is proposed. It is shown that optimally transcoded bit streams produce better picture quality than both a cascade of decoder-encoder and than a standard encoder using the original pictures, at the same reduced bit rates 相似文献
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介绍了一种新颖的DC~20GHz的4bit和5bit GaAs单片数字衰减器的设计、制造和测试结果.该衰减器的设计采用纵向思维的方法.最终得到的4bit数字衰减器的主要性能指标是:在DC~20GHz频带内,插入损耗≤3.5dB,最大衰减量15dB,衰减步进1dB,衰减平坦度≤0.2dB,衰减精度≤±0.3dB,两端口所有态的电压驻波比≤1.6,相对于参考态,衰减态的插入相移在-10°~5°以内,芯片尺寸1.8mm×1.6mm×0.1mm.5bit数字衰减器的主要性能指标是:在DC~20GHz频带内,插入损耗≤3.8dB,最大衰减量15.5dB,衰减步进0.5dB,衰减平坦度≤0.3dB,衰减精度≤±0.4dB,两端口所有衰减态的电压驻波比≤1.8,相对于参考态,衰减态的插入相移在-14°~2°以内,芯片尺寸2.0mm×1.6mm×0.1mm. 相似文献
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《Solid-State Circuits, IEEE Journal of》1985,20(2):542-547
A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm. 相似文献
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The various types of advanced television (ATV) are defined, and the most advanced type, high-definition TV (HDTV), is discussed. The present status of HDTV development in the US, Japan, and Europe is examined. Signal processing requirements for HDTV are briefly considered, and the benefits of and prospects for all-digital HDTV are explored. Video compression techniques, implementation issues, and the future of HDTV are also discussed 相似文献
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介绍了一种新颖的DC~20GHz的4bit和5bit GaAs单片数字衰减器的设计、制造和测试结果.该衰减器的设计采用纵向思维的方法.最终得到的4bit数字衰减器的主要性能指标是:在DC~20GHz频带内,插入损耗≤3.5dB,最大衰减量15dB,衰减步进1dB,衰减平坦度≤0.2dB,衰减精度≤±0.3dB,两端口所有态的电压驻波比≤1.6,相对于参考态,衰减态的插入相移在-10°~5°以内,芯片尺寸1.8mm×1.6mm×0.1mm.5bit数字衰减器的主要性能指标是:在DC~20GHz频带内,插入损耗≤3.8dB,最大衰减量15.5dB,衰减步进0.5dB,衰减平坦度≤0.3dB,衰减精度≤±0.4dB,两端口所有衰减态的电压驻波比≤1.8,相对于参考态,衰减态的插入相移在-14°~2°以内,芯片尺寸2.0mm×1.6mm×0.1mm. 相似文献
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《Electronics letters》2009,45(4):214-216
A new bit loading procedure with a successive loading structure is presented. The optimisation criterion of this scheme is to minimise the bit error rate (BER). This bit loading scheme is applied to an orthogonal frequency division multiplexing (OFDM) transmission system. Based on the measured signal-to-noise ratio (SNRn) values per subcarrier a successive loading structure is developed where the next bit is always loaded onto that subcarrier i which has the lowest BER and maximum remaining SNRi value. 相似文献
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该文提出了一种用于高速高精度电荷域流水线模数转换器(ADC)的电荷域4.5位前端子级电路。该4.5位子级电路使用增强型电荷传输(BCT)电路替代传统开关电容技术流水线ADC中的高增益带宽积运放来实现电荷信号传输和余量处理,从而实现超低功耗。所提4.5位子级电路被运用于一款14位210 MS/s电荷域ADC中作为前端第1级子级电路,并在1P6M 0.18 μm CMOS工艺下实现。测试结果显示,该14位ADC电路在210 MS/s条件下对于30.1 MHz单音正弦输入信号得到的无杂散动态范围为85.4 dBc,信噪比为71.5 dBFS, ADC内核面积为3.2 mm2,功耗仅为205 mW。 相似文献