L波段150W宽带硅脉冲功率晶体管

设计了一种称之为多晶硅覆盖树技状结构的双极型微波功率晶体管。该器件采用掺砷多晶硅发射极，同时具备有覆盖和树枝状两种图形结构的优点。器件引入扩散电阻和分布式多晶硅电阻组合而成的发射极复合镇流电阻，实现对发射极电流二次镇流，器件表现出良好的微波性能和高的可靠性。经内匹配，在L波段脉冲输出大于100W（36V），脉宽150μs，工作比10％，增益大于7．5dB，效率大于45％，器件最大输出达150W（42V）。     

异质结双极晶体管高频噪声建模及分析

提出了一个T等效异质结双极晶体管高频噪声电路模型.该模型是对通常用在硅双极晶体管中的Hawkins噪声模型进行改进得到的,主要的改进包括发射极理想因子、发射极电阻、内部BC结电容、外部BC结电容和其它寄生元素对器件噪声性能的影响.为了从等效噪声电路模型中计算出精确的噪声参数,采用了噪声相关矩阵法来计算噪声参数,从而避免了在等效电路变换中可能产生的简化和复杂的噪声测量.进一步利用该模型分析了等效电路元素对器件最小噪声系数的影响,分析计算结果和物理解释一致.同时通过基于异质结双极晶体管器件物理的公式,给出了器件参数对器件最小噪声系数的影响.     

基于Matlab的基极电流理想因子提取方法研究

采用Matlab数字分析方法,结合多晶硅发射极双极器件基极电流的构成情况,阐述了不同理想因子电流成分分离的基本原理和数学方法。利用该方法分析了多晶硅发射极双极器件在正向大电流激励下的电参数退化过程中不同理想因子基极电流的变化情况,分析了导致各电流分量变化的物理机制。该理想因子提取方法普遍适用于各类双极型器件。     

异质结双极晶体管高频噪声建模及分析

提出了一个T等效异质结双极晶体管高频噪声电路模型.该模型是对通常用在硅双极晶体管中的Hawkins噪声模型进行改进得到的,主要的改进包括发射极理想因子、发射极电阻、内部BC结电容、外部BC结电容和其它寄生元素对器件噪声性能的影响.为了从等效噪声电路模型中计算出精确的噪声参数,采用了噪声相关矩阵法来计算噪声参数,从而避免了在等效电路变换中可能产生的简化和复杂的噪声测量.进一步利用该模型分析了等效电路元素对器件最小噪声系数的影响,分析计算结果和物理解释一致.同时通过基于异质结双极晶体管器件物理的公式,给出了器件参数对器件最小噪声系数的影响.     

多晶硅发射极NPN管的辐射效应研究

为了研究多晶硅发射极双极晶体管的辐射可靠性,对多晶硅发射极NPN管进行了不同偏置条件下⁶⁰Co γ射线的高剂量率辐照试验和室温退火试验。试验结果表明,辐射后,基极电流IB显著增大,而集电极电流IC变化不大;反偏偏置条件下,IB的辐射损伤效应在辐射后更严重;室温退火后,IB有一定程度的持续损伤。多晶硅发射极NPN管与单晶硅发射极NPN管的辐射对比试验结果表明,多晶硅发射极NPN管的抗辐射性能较好。从器件结构和工艺条件方面,分析了多晶硅发射极NPN管的辐射损伤机理。分析了多晶硅发射极NPN管与单晶硅发射极NPN管的辐射损伤区别。     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

多晶硅工艺在超高频晶体管中的应用

试验使用ＬＰＣＶＤ多晶硅薄膜工艺，以掺杂多晶硅发射极结构取代传统的泡发射极Ｔｉ－Ａｌ结构，用于超高频晶体管生产中，改善了器件性能，提高了成品率和可靠性。     

SiGe/Si异质结双极晶体管工艺技术研究

介绍了多晶硅发射极双台面SiGe/Si异质结双极晶体管制作工艺流程。通过对LPCVD在n型Si衬底上外延生长SiGe合金层作为异质结双极晶体管基区、自中止腐蚀工艺制作发射区台面、多晶硅n型杂质掺杂工艺制作发射极、PtSi金属硅化物制作器件欧姆接触等工艺技术进行研究,探索出关键工艺的控制方法,并对采用以上工艺技术制作的多晶硅发射极双台面SiGe/Si异质结双极晶体管进行了I-V特性及频率特性测试。结果显示该器件饱和压降小,欧姆接触良好,直流电流放大倍数β随Ic变化不大,截止频率最高达到11.2 GHz。     

亚微米双层多晶硅自对准双极晶体管性能研究

本文采用亚微米工艺和自对准技术制作了发射区宽度分别为0.8μm和0.4μm的两种双层多晶硅自对准双极晶体管。其中采用的是深沟和LOCOS两种隔离联合的隔离方法;EB间自对准是通过均匀的高质量的SiNx侧墙实现的,EB结击穿电压高达4.5V;窄的发射区使得发射极多晶硅在发射区窗口严重堆积,引起了双极晶体管的电流增益增大,同时也降低了管子的速度。工艺和器件模拟显示,发射极多晶硅采用原位掺杂技术,双极晶体管的性能得到了很大的改善。     

多晶硅发射极晶体管的低频噪声特性

本文报导在2～2kHz的频率范围内测得的多晶硅发射极晶体管的低频噪声频谱,并论述低频噪声的产生机理。多晶硅发射极晶体管具有较常规晶体管优异的低频噪声特性而可望成为一种合适的低频低噪声器件。     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

Effects of H/sub 2/ annealing and polysilicon emitter structure on H/sub FE/ of n-p-n bipolar junction transistors

This paper presents the effects of H/sub 2/ annealing and polysilicon emitter structures on H/sub FE/ characteristics of n-p-n bipolar junction transistors. The increase of the number of H/sub 2/ annealing steps results in the device performance (H/sub FE//spl times/V/sub A/) improvement by 27.8%, due to the formation of H-Si dangling bonds, which allow the decrease of the base current. In addition, the bilayer of undoped polysilicon deposition/ion implantation and in situ doped polysilicon in the ploy emitters greatly improve the level of H/sub FE/ reliability and 1/f noise characteristic. The experimental results of H-Si dangling bond property at the polysilicon grain boundaries and polysilicon interface with the H/sub 2/ annealing steps in n-p-n bipolar junction transistor formulation will be also presented.     

Modeling the variation of the low-frequency noise in polysiliconemitter bipolar junction transistors

The variation of the low-frequency noise in polysilicon emitter bipolar junction transistors (BJTs) was investigated as a function of emitter area (A_E). For individual BJTs with submicron-sized A _E, the low-frequency noise strongly deviated from a 1/f-dependence. The averaged noise varied as 1/f, with a magnitude proportional to A_E^-1, while the variation in the noise level was found to vary as A_E^-1.5. A new expression that takes into account this deviation is proposed for SPICE modeling of the low-frequency noise. The traps responsible for the noise were located at the thin SiO₂ interface between the polysilicon and monosilicon emitter. The traps' energy level, areal concentration and capture cross-section were estimated to 0.31 eV, 6×10⁸ cm^-2 and 2×10^-19 cm ², respectively     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f_max, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively     

Effect of emitter contact materials on high-performance verticalp-n-p transistors

Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements     

A high-speed bipolar technology featuring self-aligned single-polybase and submicrometer emitter contacts

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2-μm emitter-base polysilicon contact separation. A 0.4-μm emitter width is achieved with conventional 0.8-μm optical lithography. Scaling of the emitter width of 0.3 μm has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 μm has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f_t as high as 33.8 GHz     

The influence of BF2 and F implants on the 1/f noise inSiGe HBTs with a self-aligned link base

A study is made of 1/f noise in SiGe heterojunction bipolar transistors (HBTs) fabricated using selective growth (SEG) of the Si collector and nonselective growth (NSEG) of the SiGe base and Si emitter cap. The transistors incorporate a self-aligned link base formed by BF ₂ implantation into the field oxide below the p⁺ polysilicon extrinsic base. The influence of this BF₂ implant on the 1/f noise is compared with that of a F implant into the polysilicon emitter. Increased base current noise S_IB and base current are seen in transistors annealed at 975°C, compared with transistors annealed at 950 or 900°C. At a constant collector current, both the BF₂ and F implants reduce S_IB, whereas at a constant base current, only the BF₂ implant reduces S_IB. This result indicates that the BF₂ implant decreases the intensity of the base current noise source whereas the F implant decreases the base current. The proposed explanation for the increased 1/f noise is degradation of the surface oxide by viscous flow at 975°C under the influence of stress introduced during selective Si epitaxy. The influence of the BF₂ implant on the noise is explained by the relief of the stress and hence the prevention of viscous oxide flow     

A new model for the low-frequency noise and the noise levelvariation in polysilicon emitter BJTs

Presents a new, physically-based model for the low-frequency noise in high-speed polysilicon emitter bipolar junction transistors (BJTs). Evidence of the low-frequency noise originating mainly from a superposition of generation-recombination (g-r) centers is presented. Measurements of the equivalent input noise spectral density (SIB) showed that for BJTs with large emitter areas (AE) S(I_B) is proportional to 1/f, as expected. In contrast, the noise spectrum for BJTs with submicron A_E showed a strong variation from a 1/f-dependence, due to the presence of several g-r centers. However, the average spectrum 〈S(I_B)〉 has a frequency dependence proportional to 1/f for BJTs with large as well as small A_E. The proposed model, based only on superposition of g-r centers, can predict the frequency-, current-, area-, and variation-dependency of 〈S(I_B)〉 with excellent agreement to the measured results     

超高速双层多晶硅发射极晶体管及电路

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究．这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进,主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的L型侧墙形成技术方面,它有效地减小了器件的基区面积．测试结果表明,晶体管有良好的交直流特性．在发射区面积为3μm×8μm时,晶体管的截止频率为6.1GHz．19级环振平均门延迟小于40ps,硅微波静态二分频器的工作频率为3.2GHz．