Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

Material and electrical properties of ultra-shallow p+-njunctions formed by low-energy ion implantation and rapid thermalannealing

A study of low-energy ion implantation processes for the fabrication of ultrashallow p⁺-n junctions is presented. The resulting junctions are examined in terms of four key parameters: defect annihilation, junction depth, sheet resistance, and diode reverse leakage current. In the realm of very-low-energy ion implantation, Ge preamorphization is found to be largely ineffective at reducing junction depth, despite the fact that the as-implanted boron profiles are much shallower for preamorphized substrates than for crystalline substrates. Transmission electron microscopy (TEM) analysis of residual defects after rapid thermal annealing (RTA) reveals that the use of either a preamorphization implant or the implantation of BF₂ as a B source results in residual damage which requires higher RTA temperatures to be removed. A reasonable correlation is observed between residual defect density observed via TEM and junction leakage current. It is concluded that the key to an optimized low-energy implantation process for the formation of ultrashallow junctions appears to be the proper selection of preamorphization and annealing conditions relative to the dopant implant energy     

Shallow p+n junctions formed by using a two-stepannealing scheme with low thermal budget

Shallow p⁺n junctions have been formed by directly implanting BF₂ dopant into the Si substrate and then treating the samples by an annealing scheme with low thermal budget. A junction leakage smaller than 10 nA/cm² can be achieved by an annealing scheme that employs low-temperature long-time furnace annealing (FA) at 600°C for 3 h followed by medium-temperature rapid thermal annealing (RTA) at 800°C for 30 s. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. In addition, a moderate low-temperature annealing time of about 2-3 h should be employed to optimize the shallow p⁺n junction formed by this scheme. However, the annealing process that employs medium-temperature RTA followed by low-temperature FA treatment produces worse junctions than the annealing scheme that employs long-time FA at 600°C followed by RTA at 800°C     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

High temperature formed SiGe p-MOSFETs with good devicecharacteristics

We have used a simple process to fabricate Si_0.3Ge_0.7/Si p-MOSFETs. The Si_0.3Ge _0.7 is formed using deposited Ge followed by 950°C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm²/Vs is obtained from the Si_0.3Ge_0.7 p-MOSFET that is ~two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Å Si_0.3Ge_0.7 thermal oxide grown at 1000°C has a high breakdown field of 15 MV/cm, low interface trap density (D_it) of 1.5×10¹¹ eV^-1 cm^-2, and low oxide charge of 7.2×10¹⁰ cm^-2. The source-drain junction leakage after implantation and 950°C RTA is also comparable with the Si counterpart     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

Optimization of the germanium preamorphization conditions forshallow-junction formation

Shallow p⁺-n and n⁺-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3×10¹⁴ to 1×10¹⁵ cm^-2. p ⁺-n junctions were formed by 10-keV boron implantation at a dose of 1×10¹⁵ cm^-2. Arsenic was implanted at 50 keV at a dose of 5×10¹⁵ cm^-2 to form the n⁺-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1×10¹⁵ cm^-2 germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p⁺-n and n⁺-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized     

Ultra-shallow junction formation using silicide as a diffusionsource and low thermal budget

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide processing) of 45-nm CoSi₂ films (3.5 Ω/□) using a low thermal budget. The best junctions of either type were made by moderate 10-s RTA (rapid thermal annealing) at 800°C, where the total junction depth, counting the silicide thickness, is believed to be under 60 nm. Diffusion-limited current predominated down to 50°C in junctions made under these conditions. The initial implantation energy had only a minor effect on the junction leakage, where shallower implants required slightly higher temperatures to form low leakage diodes, resulting in diodes which were somewhat more susceptible to shorting during silicide agglomeration at high temperatures. The ITS scheme, where dopant is implanted slightly beyond the silicide, gives an equally low leakage current. Nevertheless, the ITS scheme gives deeper junctions than the SADS process, and it is difficult to control the position of the ITS junction due to silicide/silicon interface fluctuations     

The reverse anneal of junction characteristics in forming shallow p+-n junction by BF2+ implantation intothin Co films on Si substrate

Silicided shallow p⁺-n junctions, formed by BF₂ ⁺ implantation into thin Co films on Si substrates and subsequently annealed, showed a reverse anneal of junction characteristics in the temperature range between 550 and 600°C. The reverse anneal means behavior showing degradation of the considered parameters with increasing annealing temperature. A higher implant dosage caused a more distinct reverse anneal. The reverse anneal of electrical characteristics was associated with the reverse anneal of substitutional boron. A shallow p⁺-n junction with a leakage current density lower than 3 nA/cm₂, a forward ideality factor of better than 1.01, and a junction depth of about 0.1 μm was achieved by just a 550°C anneal     

A novel self-aligned TiN formation by N2+implantation during two-step annealing Ti-salicidation for submicrometerCMOS technology application

A new technology of self-aligned TiN/TiSi₂ formation using N₂⁺ implantation during two-step annealing Ti-salicidation process has been developed. The formation of TiN was confirmed by RBS analysis. The leakage currents of n⁺/p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi₂ contact is 1.2 nA/cm² at -5 V, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500°C. Thus, TiN formed with this technology process is suggested as a very effective barrier layer between TiSi₂ and Al for submicron CMOS technology applications     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Self-aligned silicided (PtSi and CoSi2) ultra-shallow p+/n junctions

Ultra-shallow p+/n junctions (<100 nm) demonstrating excellent I-V characteristics have been fabricated with self-aligned PtSi. Junctions were formed by rapid thermal annealing (RTA) 〈100〉 Si preamorphized with Sn+ and implanted with BF2+. Subsequently, low-temperature RTA in N2of sputter-deposited Pt produced a 55-nm-thick PtSi layer possessing a remarkably smooth surface and interface, and demonstrating excellent resistance to the aqua regia etch solution. The silicided junctions displayed a sheet resistance of 14 Ω/sq with less than -2-nA . cm^-2reverse-bias leakage at -5 V. In a comparative scheme, similar junction characteristics were obtained using a self-aligned 39-nm-thick CoSi2overlayer.     

Rapid thermal annealing of BF2+implanted, preamorphized silicon

BF2+is implanted into preamorphized silicon and annealed using radiative, incoherent rapid thermal annealing (RTA). Ion channeling tails are eliminated ans electrical activity of the entire profile is obtained during the solid-phase epitaxial regrowth of the amorphous silicon. This work shows that the shallow electrically active profiles are indistinguishable from the as-implanted profiles over the entire impurity depth distribution. Sheet resistance and SIMS data illustrate the effects. The RTA approach, in combination with preamorphized silicon, may have application to submicron MOS technology when junction depths <0.15 µm are required.     

Process and device characterization for a 30-GHz fT submicrometer double poly-Si bipolar technology using BF2-implanted base with rapid thermal process

Process and device parameters are characterized in detail for a 30-GHz f_T submicrometer double poly-Si bipolar technology using a BF₂-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050°C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7×10^-7 Ω-cm², while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors     

New Ti-SALICIDE process using Sb and Ge preamorphization forsub-0.2 μm CMOS technology

A new process for thin titanium self-aligned silicide (Ti-SALICIDE) on narrow n⁺ poly-Si lines and n⁺ diffusion layers using preamorphization implantation (PAI) with heavy ions of antimony (Sb) and germanium (Ge) has been demonstrated for application to 0.2-μm CMOS devices and beyond. Preamorphization enhances the phase transformation from C₄₉Ti_xSi _x to C₅₄TiSi₂ and lowers the transformation temperature by 80°C so that it occurs before conglomeration in narrow lines. Preamorphization by Sb and Ge implantation yields better results than that by As. The sheet resistance of TiSi₂ on heavily As doped poly-Si lines are 3.7 Ω/□ and 3.8 Ω/□ for the samples preamorphized by Ge and Sb implantations even with line width down to 0.2 μm. There is less leakage in the Ti-SALICIDE diode with preamorphization than without it. The probable reasons and mechanisms are discussed     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

Formation of TiN/TiSi2/p+-Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

A low temperature method of fabricating conductive (3.5 Ω/ sq.) p⁺/n junction diodes possessing excellentI-Vcharacteristics with reverse-bias leakage less than -3 nA.cm^-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV¹¹B+through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N2ambient simultaneously forms a 0.36-µm deep p⁺/n junction and a 0.063-µm thick bilayer of TiN and TiSi2with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi2and Al.     

Silicon preamorphization and shallow junction formation for ULSI circuits

The effects of preamorphization of silicon by¹⁹F,²⁸Si and⁷⁴Ge implants preceding¹¹B implants have been investigated in this work and compared with BF₂ molecular implants. For shallow boron implanted layers less than 0.2 μm deep, the beam purity of BF₂ implants is crucial as well as proper preamorphization of the silicon to eliminate any inadvertent channeling. Preamorphization of silicon can be achieved with either⁷⁴Ge,²⁸Si or¹⁹F implants. Data from SIMS, TEM, RBS and diode leakage current measurements have all consistently shown that the best results are obtained with⁷⁴Ge preamorphization, followed by²⁸Si- and¹⁹F-preamorphization. RTA of preamorphized silicon at 1000° C for 10s in a dry argon ambient is preferred for shallow junctions. Furnace anneals at 950° C for 45 min of⁷⁴Ge preamorphized samples have resulted in practically perfect PN junctions.