Current-source a-Si:H thin-film transistor circuit for active-matrix organic light-emitting displays

In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as /spl sim/3 V, the output current variations can be less than 1 and 5% for high (/spl ges/0.5 /spl mu/A) and low (/spl les/0.1 /spl mu/A) current levels, respectively. This circuit can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs).     

High-performance 1.06-/spl mu/m selectively oxidized vertical-cavity surface-emitting lasers with InGaAs-GaAsP strain-compensated quantum wells

We present the first room-temperature continuous-wave operation of high-performance 1.06-/spl mu/m selectively oxidized vertical-cavity surface-emitting lasers (VCSEL's). The lasers contain strain-compensated InGaAs-GaAsP quantum wells (QW's) in the active region grown by metalorganic vapor phase epitaxy. The threshold current is 190 /spl mu/A for a 2.5/spl times/2.5 /spl mu/m/sup 2/ device, and the threshold voltage is as low as 1.255 V for a 6/spl times/6 /spl mu/m/sup 2/ device. Lasing at a wavelength as long as 1.1 /spl mu/m was also achieved. We discuss the wavelength limit for lasers using the strain-compensated QW's on GaAs substrates.     

A driving scheme for active-matrix organic light-emitting diode displays based on feedback

A scheme of driving active matrix organic light emitting diode (AMOLED) displays with hydrogenated amorphous silicon (a-Si) thin-film transistors (TFTs) is presented. By sending a feedback voltage from each pixel to a column driver during the programming cycle, the driving scheme can compensate for the instability of the TFTs, in particular, the shift in the threshold voltage. Measurement results show no change in the OLED current in the presence of a 1.3-V shift in the threshold voltage. Based on circuit analysis, a simple lead compensator and an accelerating pulse were employed to achieve fast pixel programming for a wide range of OLED currents. Simulation results show a programming time of less than 70 /spl mu/s for OLED currents as low as 50 nA.     

1.5 V four-quadrant CMOS current multiplier/divider

A low voltage CMOS four-quadrant current multiplier/divider circuit is presented. It is based on a compact V-I converter cell able to operate at very low supply voltages. Measurement results for an experimental prototype in a 0.8 /spl mu/m CMOS technology show good linearity for a /spl plusmn/15 /spl mu/A input current range and a 1.5 V supply voltage.     

GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

Performance enhancement of offset gated polysilicon thin-film transistors

Simple offset gated n-channel polysilicon thin film transistors (TFTs) of channel length L=10 /spl mu/m were investigated in relation to the intrinsic offset length /spl Delta/L and the polysilicon quality. For /spl Delta/L/spl les/1 /spl mu/m, the device parameters such as threshold voltage, subthreshold slope and field effect mobility are improved, while the leakage current remains unchanged. In TFTs with /spl Delta/L>1 /spl mu/m, the leakage current decreases with increasing the offset length. When the polysilicon layer is of high quality (large grain size and low intra-grain defect density), the leakage current is completely suppressed without sacrificing the on-current in TFT's with offset length of 2 /spl mu/m.     

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

Electrically-pumped vertical-cavity lasers with Al/sub x/O/sub y/-GaAs reflectors

We have fabricated the first electrically-pumped vertical-cavity surface-emitting lasers (VCSELs) which use oxide-based distributed Bragg reflectors (DBRs) on both sides of the gain region. They require a third the epitaxial growth time of VCSELs with semiconductor DBRs. We obtain threshold currents as low as 160 /spl mu/A in VCSELs with an active area of 8 /spl mu/m/spl times/8 /spl mu/m using a two quantum well InGaAs-GaAs active region. By etching away mirror pairs from the top reflector, quantum efficiencies as high as 61% are attained, while still maintaining a low threshold current of 290 /spl mu/A.