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基于阈算术代数系统理论,以和图为指导,分析施密特反相器的阈值可控开关,对三值电流型CMOS施密特反相器进行设计。Hspice仿真结果表明,该电路具有正确的逻辑功能和良好的瞬态特性,阈算术代数系统设计得到进一步的完善,三值施密特反相器设计更加简单直观。 相似文献
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This paper presents a 1-Gb/s optical receiver with full rail-to-rail output swing realized in a standard 0.7-μm CMOS technology. The receiver consists of a 1-kΩ transimpedance preamplifier followed by a postamplifier based on a biased inverter chain. The latter performs both a linear and a limiting amplification. The automatic biasing of the chain is provided through an offset tolerant replica circuit. The receiver requires no external components or biasing voltages. It is designed for a relatively large 0.8-pF input capacitance and is fed from a single 5-V power supply. These properties make the circuit suitable for a commercial environment. A sensitivity of 10 μA was measured at 1 Gb/s. The complete receiver, including all biasing and replicas, consumes approximately 100 mW from the 5-V supply. When powered from a 3.3-V supply, a maximal bit rate of 600 Mb/s is achieved, while the power consumption is reduced to approximately 26.5 mW 相似文献
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通过对CMOS数字电路器件及RF脉冲扰乱效应的模拟分析,比较了注入不同频率与功率的RF扰乱脉冲时对CMOS反相器输出逻辑电平扰乱甚至翻转的效应过程。 相似文献
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提出了一种具有新型像素结构的大动态范围CMOS图像传感器,通过调整单个像素的积分时间来自适应不同的局部光照情况,从而有效提高动态范围。设计了一种低延时、低功耗、结构简单的新型pixel级电压比较器及基于可逆计数器的时间-电压编码电路。采用0.6μm DPDM标准数字CMOS工艺参数对大动态范围像素单元电路进行仿真,积分电容电压Vcint与光电流呈良好的线性关系,其动态范围可达126dB。在3.3V供电电压下,单个像元功耗为2.1μW。 相似文献
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一个128×128CMOS快照模式焦平面读出电路设计 总被引:3,自引:0,他引:3
本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构——DCA(Direct-injection Charge Amplifier)结构.该结构像素电路仅用4个MOS管,采用特殊的版图设计并用PMOS管做复位管,既可保证像素内存储电容足够大,又可避免复位电压的阈值损失,从而提高了读出电路的电荷处理能力.由于像素电路非常简单,且该结构能有效消除列线寄生电容Cbus的影响,因此该结构非常适用于小像素、大规模的焦平面读出电路.采用DCA结构和1.2μm双硅双铝(DPDM-Double-Poly Double-Metal)标准CMOS工艺设计了一个128×128规模焦平面读出电路试验芯片,其像素尺寸为50×50μm2,电荷处理能力达11.2pC.本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的HSPICE仿真结果和试验芯片测试结果. 相似文献
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三值电压型CMOS施密特电路研究 总被引:4,自引:0,他引:4
首先对二值CMOS施密特电路的设计思想进行了分析,指出设计施密特电路的关键为阈值控制电路。根据三值CMOS电路有两个信号检测阈的特点,提出了通过文字电路将两个检测阈分离后进行分别控制并由文字电路的输出去控制CMOS传输门的设计方法,由此设计了三值CMOS施密特反相器。PSPICE模拟证明了所设计的电路具有理想的施密特电路功能 相似文献
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根据有关对称三进制逻辑的资料,结合CMOS电路生产工艺特点,设计并试制了对称三值逻辑CMOS系列电路。其中包括倒相器与非门、或非门、变形反相器和T门共五种基本电路。本文叙述了设计方案,生产工艺及结果讨论。 相似文献
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《Solid-State Circuits, IEEE Journal of》1979,14(6):1010-1019
Using voltage inverter switches, exact analog sampled-data equivalents of Rs, Ls and Cs, as well as unit elements, can be designed with MOS capacitors and switches. Due to the underlying bilinear transformation, no limitation other than the Nyquist limit is imposed on the ratio of corner to sampling frequency. For an nth order filter, the number of voltage inverter switches is (n+1)/4 to (n+1)/2. A 3.4 kHz third-order Chebyshev low-pass CMOS circuit is described in detail. It uses only one voltage inverter switch implemented by a switched op amp integrator. The sampling frequency is 24 kHz, the dynamic range exceeds 70 dB and the chip area is 1.2 mm/SUP 2/. A CMOS voltage inverter switch, which has zero DC power and occupies only 0.09 mm/SUP 2/ is presented, whose dynamic range exceeds 85 dB. This allows low power switched capacitor filters without operational amplifiers and with a frequency capability approaching the megahertz range. 相似文献
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We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications. 相似文献
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高速高精度ADC是CMOS图像传感器中的重要部分。随着工艺的进步,低功耗设计已经吸引了很多人的注意。为了在没有降低表现的情况下控制功耗,在本设计采用相同结构放大器共用相同的偏置电路技术,并且采用了共源共栅补偿技术来降低功耗。噪声和不匹配也是流水线ADC中重要的误差源,因此采用了Matlab对这两者进行了仔细的计算和系统仿真。在本文中,提出了一个10位50MS/s的 流水线ADC核心。这个设计可以用于大像素规模的CMOS图像传感器。本设计在表现和功耗上取得了很好的平衡。 相似文献
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Shyh-Yih Ma Liang-Gee Chen 《Solid-State Circuits, IEEE Journal of》1999,34(10):1415-1418
A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm2 of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply 相似文献
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根据传统电流源结构,设计了一种启动电流为0的CMOS低功耗电流源。电流源的启动电路仅采用一个耗尽型MOS管,电路正常工作后启动电路会自动关断。仿真结果显示电路正常工作后启动部分消耗的电流基本降为0,整个电路功耗24.9μW。这种结构降低了整个电路的功耗,大大节省了芯片面积。电路基于TSMC0.18μm CMOS工艺,电源电压1.8V,仿真软件为Hspice。 相似文献