超快速逻辑分析仪

U4154A AXIe逻辑分析仪具有业界领先的状态捕获速率：68通道时为4Gb/s,136通道时为2.5Gb/s;并且可以在业界最小的100ps×100mV眼张开度上稳定地捕获数据。U4154A AXIe逻辑分析仪模块配合相关探头和功能强大的分析软件可以为DDR存储系统、高速ASIC、模数转换器和工作速率高达4Gb/s的FPGA的测试提供关键性能保证。U4154A的专利眼图扫描技术只用很短时间就可以完成DDR系统全部信号的信号完整性的扫描。     

测试和测量

超快速逻辑分析仪U4154A AXIe逻辑分析仪具有业界领先的状态捕获速率:68通道时为4Gb/s,136通道时为2.5Gb/s;并且可以在业界最小的100ps×100mV眼张开度上稳定地捕获数据。U4154A AXIe逻辑分析仪模块配合相关探头和功能强大的分析软件可以为DDR存储系统、高速ASIC、模数转换器和工作速率高达4Gb/s的FPGA的测试提供关键性能保证。U4154A的专利眼图扫描技术只用很短时间就可以完成DDR系统全部信号的信号完整性的扫描。B4622A DDR2/3协议一致性测试和分析     

光纤通信系统的发展和展望

向40Gb/s高速率发展从过去20多年的电信发展史看,光纤通信发展始终在按照电的时分复用（TDM）方式进行,每当传输速率提高4倍,传输每个比特的成本大约下降30-40%;因而高比特率系统的经济效益大致按指数规律增长。目前10Gb/s系统已大批量装备网络,不少电信公司实验室已开发出40Gb/s的系统,预计不久将开始实用化。从网络应用看,带10Gb/s接口的路由器已经问世,随着这些路由器的大量应用,为了提高核心网的效率和功能,核心网的单波长速率向40Gb/s方向演进是合乎逻辑的。160Gb/s速率ETDM和640Gb/s速率OTDM的传输试验也已获成功,…     

声纳信号处理中UDP协议数据传输研究与设计

为了在声纳系统中通过以太网口进行大批量、高速率的数据传输处理,在FPGA中硬件实现了嵌入式UDP协议栈,完成了架构设计、软件仿真验证及硬件实现。用FPGA硬件实现UDP协议栈,加速了网络数据处理能力,使信号传输速率达到了80MB/s,实现了千兆级通信,很好地提高了声纳系统中数据传输速率和系统性能。同时,用FPGA硬件实现UDP协议,栈减小了PCB版图面积和布局布线复杂度,提高了开发效率,有效地降低了开发成本。     

2.5Gb/s GaAs MESFET定时判决电路

设计了2.5Gb/s光纤通信用耗尽型GaAs MESFET定时判决电路.通过SPICE模拟表明恢复的时钟频率达2.5GHz,判决电路传输速率达2.5Gb/s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号,传输速率达2.5Gb/s.     

40Gb/s技术的回顾与展望

目前,呈爆炸式增长的互联网业务量对数据通信系统提出了严峻的挑战。快速时分复用(TDM)和密集波分复用(DWDM)的综合应用方案应运而生,它通过扩展光放大器的增益带宽来满足网络需求;另一方面,互联网路由器和以太网传输技术方面的研究进展也很显著。高端路由器、千兆以太网交换机的接口速度已经提高到了10Gb/s。中国电信已经开始在上海到杭州的Cisco路由器上采用了10G接口。在北美,也已经出现了直接租用10G带宽的客户。要使网络实现更高速率的传输,骨干网层面必然需要更大的传输颗粒——40Gb/s。40Gb/s作为10Gb/s的后继传输速率,可以满…     

高精度色散管理实现160Gb/s光时分复用信号100km稳定无误码传输

在160 Gb/s 100 km光时分复用(OTDM)通信系统中,色散是影响系统性能的主要因素。为减小由此带来的信号波形的失真,进行了理论分析与研究,并做了相应的实验加以验证。传输链路采用混合补偿方式,精确补偿色散与色散斜率,优化传输链路色散图谱及各点工作功率,有效抑制非线性效应,实现高精度色散管理,提升系统的整体性能。使用500 GHz高速示波器,调整传输链路光纤的长度精确到10 m,并准确观测各环节实验结果。系统既没有使用前向纠错技术,也没有进行偏振模色散(PMD)补偿,仅仅通过高精度色散管理实现了160 Gb/s光时分复用信号100.25 km稳定无误码(误码率小于10-12)传输。     

基于串并收发器技术的照射制导2.5 Gbit/s光电系统

针对当前照射制导设备数据传输能力存在的问题，文章提出了一种基于串并收发器技术、传输速率为2.5 Gbit/s的光电通信系统设计。该设计以串并收发器为核心，采用光纤传输与现场可编程门阵列(FPGA)软件结合的方式对网络报文控制数据、状态采样数据和同步时序信号等不同速率和接口形式的数据进行组帧和解帧处理，最终实现了高速光电系统的通信。测试结果表明，该系统大幅提升了阵面数据信息的传输和处理速率，同时降低了传统阵面与地面通信系统的硬件设备数量和繁杂度，突破了阵面与地面间的传输距离限制。     

统筹考虑满足数据率要求

不久前人们还认为铜背板系统已走到了极限，要取得2.5 Gb/s的数据率需要用光来实现。而今天，采用传统的铜技术照例能实现2.5 Gb/s传输速率。目前设计人员还能获得5 Gb/s乃至10 Gb/s的数据传输率。在高速率的设计中，必须把有源器件、连接器、PCB和系统结构间互作用当作一个紧密结合的整体来考虑。增强性能跨背板通信器件的选择是集成化系统设计过程的第一步。背板收发器使系统内部子卡间可以互相通信。它们接收进入数据的容限常常用在接收机端测得的睁眼来表示。随着元器件制造商向更高数据率的发展，性能增强技术受到格外关注。在收发…     

基于LVDS的高速数据交换引擎IP核设计

设计了一种基于LVDS的高速数据交换引擎IP核,并详细阐述了在FPGA上的实现原理和关键设计.该IP核能广泛适用于低速、高速FPGA中,测试结果表明,IP核的逻辑功能正确,可适应从spartan3A器件上时钟频率150MHz,300Mb/s数据传输速率(1位模式,4位模式下达到1.2Gb/s),到Virtex6器件上时钟频率500MHz,1Gb/s数据传输速率(1位模式,4位模式下达到4Gb/s).     

不同调制格式对400 Gb/s通信系统传输容量和距离的影响

单载波400 Gb/s传输是下一代通信系统的主要应用速率,为提高此速率通信在实际工程应用中的传输效率,理论分析了高速通信系统中不同调制方式与传输谱宽的关系,基于16阶正交幅度调制(16QAM)、16QAM/32QAM混传、32QAM、32QAM/64QAM混传和64QAM 5种不同调制格式,对400 Gb/s传输系统的单波入纤功率、传输容量和传输距离进行了实验研究,实验结果表明调制格式混传模式和单传模式对系统传输容量和传输距离存在着明显的差异。     

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication bandwidth and concurrency of small-scale digital systems. To improve the overall system performance without increasing communication resources and complexity, this paper presents a cost-effective interconnect architecture, communication protocol, and signaling technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SSCDMA-I) enables dual concurrent transactions on a single wire line as well as flexible input/output (I/O) reconfiguration. The SSCDMA-I utilizes 2-bit orthogonal CDMA coding and a variation of source synchronous clocking for multilevel superposition; a single 3-level SSCDMA-I line operates as if it consists of dual virtual time-multiplexed interconnects, which exploits communication parallelism with a reduced number of pins, wires, and complexity. The unique multiple access capability of the SSCDMA-I improves real-time communication between multiple semiconductor intellectual property (IP) blocks on a shared link or bus by reducing the bus contention interference from simultaneous traffic requests and by taking advantage of shorter request latency. The prototype transceiver chip is implemented in 0.18-m CMOS and the 10-cm test PC board system achieves an aggregate data rate of 2.5 Gb/s/pin between four off-chip (2Tx-to-2Rx) I/Os.     

基于FPGA的高速串行光纤图像传输检测平台

采用FPGA作为高速串行光纤图像传输系统的核心,利用Rocket IO串行传输技术,根据自定义的光纤图像传输协议,搭建了检测平台;在EDK开发工具下,通过对FPGA进行SOPC设计,实现检测平台的软件设计,并实时输出检测结果。阐述了检测平台的系统总体设计思想,对检测平台的硬件设计、软件设计、SOPC设计、高速串行光纤图像传输技术进行了详细说明,并对自定义的光纤图像传输协议、检测实验等进行介绍。经过实验测试结果表明,检测平台工作在3.125Gb/s的串行传输速率上,平台运行稳定、可靠;利用该检测平台,实现了图像经过板件间高速串行传输的检测、经过系统级间串行传输的检测,以及经过多个串行传输系统后的检测,达到了检测的目的。     

万兆以太网技术的研究与实现

为了提高通信系统的数据吞吐量,增加系统集成度,在IEEE 802.3ae标准的基础上,对万兆以太网技术进行了研究并实现。万兆以太网技术是基于FPGA实现的,FPGA完成的主要工作包括:完成与上层软件的指令和数据交互、数据的组帧/解帧、与物理层的接口管理等。物理层发送端主要完成数据对齐、变速并加扰、并串转换等工作,将串行数据发送给光电转换模块,接收端正好相反。经过万兆以太网标准仪器测试,传输速率达到了10 Gb/s,大大提高了系统间数据传输的速度和效率,简化了系统结构。     

System performance evaluation of the FSA submarine opticalamplifier system

The FSA submarine optical amplifier system developed for commercial use is designed to transmit 2.5 and 10 Gb/s signals flexibly; its repeater spacing is 90 km. It contains six line pairs to yield a maximum transmission capacity of 60 Gb/s. Its system configuration, and the characteristics of its fibers and optical amplifiers, which realize effective dispersion and optical passband management, are introduced. We discuss its performance with regard to the parameters significant in optically amplified transmission: evolution of zero dispersion wavelength (ZDW), polarization mode dispersion (PMD), and fiber nonlinearity induced impairments. Signal-to-noise ratios (SNR's) for 2.5 and 10 Gb/s signal transmission are measured and the improvements offered by polarization scrambling are also discussed. Finally, ZDW, PMD, and SNR characteristics of the system after installation are reported     

基于多载波复用多模光纤通信系统的设计与分析

分析了多模光纤高频带通区域的传输特性,提出一种基于多载波复用的多模光纤通信系统.对该系统的传输特性进行了分析和仿真,结果表明:系统所用载波数是影响系统性能的重要因素;选取合适载波数,该系统可将10.2Gb/s的数据传输1km、将2.5Gb/s的数据传输4.2km;增大激光器的发送功率可以显著增加系统的传输距离.     

All-Raman ultralong-haul single-wideband DWDM transmission systems with OADM capability

In this paper, we present a comprehensive experimental investigation of an all-Raman ultrawide single-band transmission system for both 10 and 40 Gb/s line rates. Enabling technologies include forward-Raman pumping of the transmission fiber, counter-Raman pumping of the fiber spans and dispersion compensation modules, wideband dispersion, and dispersion-slope compensation, and modulation formats resistant to both linear and nonlinear impairments. Ultralong-haul (ULH) 128/spl times/10 Gb/s return-to-zero (RZ) and ultrahigh-capacity (UHC) 64/spl times/40 Gb/s carrier-suppressed (CS) RZ transmission are demonstrated for commercially deployed fiber types, including both standard single-mode fiber (SSMF) and nonzero dispersion shifted fibers (NZDSF). The span losses of 23 dB (NZDSF) and 20 dB (SSMF) are consistent with those encountered in terrestrial networks. The optical reaches for 10 Gb/s rate are 4000 km (NZDSF) and 3200 km (SSMF). Using the same distributed Raman amplification (DRA) scheme, UHC over 2.5 Tb/s at a 40-Gb/s per channel rate is also demonstrated for all of the tested fiber types and for optical reaches exceeding 1300 km. We then study the impact of including optical add/drop modules (OADMs) in the transmission system for both 10 and 40 Gb/s channel rates. System performance is characterized by the system margin and the transmission penalty. For all of the experiments shown in this paper, industrial margins and small transmission penalties consistent with operation in commercially deployable networks are demonstrated, showing the feasibility of practical implementation of all-Raman amplified systems for ULH and UHC optical backbones. Attractive features of single-wideband transmission enabled by DRA include simplicity of design, flexible gain and gain-ripple control, good noise performance, and a small system footprint.     

一种提高FPGA片间通信稳定性的校验协议研究

随着FPGA（Field Programmable Gate Array）在大型系统中得到越来越广泛的应用,单片FPGA往往难以胜任全部工作,多片FPGA之间进行高速稳定通信成为了该领域的一个研究热点。为此设计了一种基于低压差分信号（low voltage differential signal,LVDS）可用于FPGA片间高速稳定通信的校验协议,该协议在常规LVDS通信的基础上进行多轮多路校验,以提高传输可靠性。基于该协议,搭建了一套由两片Xilinx 7系列FPGA构成的9通道LVDS通信测试系统。其中1个通道用于同步时钟,另外8通道用于校验和通信。经过长时间高低温测试,在保证单路传输速率达1.2 Gb/s的情况下,相对于常规LVDS通信,误码率大大降低。     

中国移动对于100-Gb/s WDM系统的需求和策略

In recent years, the booming bandwidth demands of dedicated mobile services have driven the rapid development of optical transport networks (OTNs). Through the in-novative use of emerging coherent optical communication technology and the advancement of microelectronics technology, the new-generation 100Gb/s transport technology offers a high line rate and unprecedented resilience to optical transmission impairments. This paper overviews the bandwidth demands of China Mobile driven by the upcoming rollout of Time Division-Long Term Evolution (TD-LTE) and presents the 100Gb/s trials at China Mobile that were used to verify the performance of a 100Gb/s system. China Mobile’s considerations, which were based on the trial results, regarding the deployment of 100Gb/s transport systems are introduced, and the requirements of China Mobile for the evolution of 100Gb/s transport systems are summarized.     

Prescaled clock recovery based on small timing misalignment of datapulses

A simple and robust prescaled clock recovery technique is analyzed and demonstrated. An electrical clock is extracted from an ultra-high-speed time-division multiplexed (TDM) RZ signal using a “classic” approach to clock recovery with a detector and a bandpass filter (BPF). A subharmonic tone at the base rate frequency is generated by inducing a small misalignment between adjacent pulses in the transmitted data. The subharmonic tone is recovered as a clock signal at the receiver. Numerical calculations clarify the effect of filter bandwidth, word length, and strength of timing shift on the received timing jitter. Furthermore, it is found numerically that correlated TDM channels will decrease the jitter of the recovered clock considerably. A clock recovery circuit is implemented into an experimental 40 Gb/s and 80 Gb/s optical TDM (O-TDM) system without any observed penalty. Measurements of the timing jitter of the recovered prescaled clock have been performed to verify the numerical results. A 10 GHz clock signal with subpicosecond root-mean-square timing jitter is recovered from a 40-Gb/s O-TDM sequence without a phase-locked loop (PLL) configuration. By using a PLL-configuration, the timing jitter is reduced further by 50%. A discussion on the influence on transmission capacity is performed in general and for nonlinear optical communication systems in particular