A 5-GHz SiGe HBT return-to-zero comparator for RF A/D conversion

This paper presents a monolithic comparator implemented in a 0.5-μm SiGe heterojunction bipolar transistor (HBT) process. The SiGe HBT process provides HBT npn transistors with maximum f_T over 40 GHz and f_max over 55 GHz. The comparator circuit employs a resettable slave stage, which was designed to produce return-to-zero output data. Operation with sampling rates up to 5 GHz has been demonstrated by both simulation and experiments. The comparator chip attains an input range of 1.5 V, dissipates 89 mW from a 3-V supply, and occupies a die area of 407×143 μm². The comparator is intended for analog-to-digital (A/D) conversion of 900 MHz RF signals     

基于InP-DHBT的20 GHz的超高速比较器

采用截止频率fT为170 GHz的InP-DHBT工艺,我们设计并制作了一个超高速主从电压比较器。整个芯片的面积（包括焊盘）是0.75?1.04 mm2,在-4V的单电源电压下消耗的功耗是440mW（不包括时钟产生部分）。整个芯片包含了77个InP DHBTs。比较器的尼奎斯特测试到了20GHz,输入灵敏度在10 GHz采样率的时候是6mV,在20 GHz的时候是16 mV。据我们所知,这在国内还是第一次在单片上集成超过70个InP DHBTs的电路,也是目前国内具有最高采样率的比较器。     

CMOS charge-transfer preamplifier for offset-fluctuationcancellation in low-power A/D converters

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved     

A self-aligned gate III-V heterostructure FET process forultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8×8 multiplier/accumulator, and a 4500-gate 16×16 complex multiplier have been demonstrated using enhancement-mode n⁺ -(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1-μm gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 μm of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained     

Demonstration of RSFQ digitizer on a multichip module

A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-μm Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 × 5 mm chip was flip-chip mounted on a 10 × 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about ±6% at 10 GHz     

A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in0.7-μm CMOS

A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz     

100-GHz high-gain InP MMIC cascode amplifier

A high-gain InP monolithic millimeter-wave integrated circuit (MMIC) cascode amplifier has been developed which has 8.0 dB of average gain from 75 to 100 GHz when biased for maximum bandwidth, and more than 12 dB of gain at 80 GHz at the maximum-gain bias point, representing the highest gains reported to date, obtained from MMICs at W band (75-100 GHz). Lattice-matched InGaAs-InAlAs high-electron-mobility-transistors (HEMTs) with 0.1-μm gates were the active devices. A coplanar waveguide (CPW) was the transmission medium for this MMIC with an overall chip dimension of 600×500 μm     

High-speed divide-by-4/5 counter for a dual-modulus prescaler

A new high-speed divide-by-4/5 counter is developed. Based on this divide-by-4/5 counter, a 3 V 2 M ~1.1 GHz dual-modulus divide-by-128/129 prescaler fabricated with 0.6 μm CMOS technology is presented. Its maximum operating frequency of 1.11 GHz with power consumption of 19.2 mW has been measured at a 3 V supply voltage. In addition, for a power supply of 1.5 V, the circuit consumed 2.67 mW at a maximum input frequency of 520 MHz     

A CCD frequency prescaler for broadband applications

A broadband, compact, and power-efficient frequency prescaler based on two-phase CCDs (CCD-FP) is described. It is similar in operation to flip-flop-based divide-by-N circuits. However, the maximum operating frequency is determined by the charge transit time between CCD electrodes, rather than the propagation delay of a logic gate in which circuit parasitics limit performance, so that relatively large gate length CCD electrodes (1 μm) can be used in a millimeter-wave device. A prototype CCD-FP has been implemented in a GaAs-AlGaAs modulation-doped CCD (MD-CCD) technology and demonstrated at frequencies up to 18 GHz. The CCD-FP has a constant input voltage sensitivity as a function of input frequency and the output signal is phase locked to the input. Expansion of the prescaler modulus incurs no penalty in speed of operation and very modest increases in power dissipation, circuit complexity, and chip area. In conjunction with PISCES two-dimensional transient simulations of the 1-μm MD-CCD, SPICE analysis predicts that an InGaAs-based CCD-FP is capable of operating frequencies approaching 100 GHz     

High-speed, highly sensitive OEIC using clocked vertical BJT'sphotoDarlington in CMOS technology

A novel CMOS synchronized photoreceiver is proposed for conversion of optical input pulses to digital output signals. The photoreceiver circuit consists of a photoDarlington used as a detector of input light followed by a current-mirror comparator used as a converter to electronic signals. A combination of two p-n-p vertical CMOS bipolar junction transistors controlled by an external clock is designed to achieve the first clocked photoDarlington structure. The generated photocurrent is amplified and digitized by the current-mirror comparator in a return to-zero format. The synchronized photoreceiver has been implemented in a standard digital 0.7 μm, 5 V n-well CMOS technology with an effective area of 100×60 μm². It was measured to operate at 100 MHz with an external input light of 13.3 fJ/pulse (-18.8 dBm/beam)     

GaAs MESFET logic with 4-GHz clock rate

Monolithic digital ICs with GaAs MESFETs have been built and operated at clock frequencies up to 4.5 GHz. The fabrication process uses selenium-implanted n-channels and a two-level Cr-Pt-Au metallization with 1-/spl mu/m linewidth and 1-/spl mu/m alignment tolerances. NOR gates with 86-ps propagation delay and 40-mW power consumption have been realized. Binary frequency dividers have been designed with master-slave flip-flops operating from dc up to an average maximum frequency of 4 GHz. In addition, more complex circuits have been integrated on single chips. A general-purpose octal counter with input gating and output buffering and an 8-bit multiplexer/serial data generator exhibit stable and reliable operation.     

A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300×4000 μm², including the passive loop filter     

Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications

A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems has been designed based on a 21 GHz f _T 0.4 μm Si bipolar process. The circuit provides features such as bit-rotation control, clock enable control, outputs aligned in time, and phase aligner for clock signals. It operates up to 14 Gb/s (14 GHz) with a phase margin of ⩾250°. The power consumption is 2 W with a -4.5 V supply. 1:16-demultiplexer operation is demonstrated on the basis of 1:4-demultiplexer IC's at 10 Gb/s     

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

A comparator in a low-power 65-nm complementary metal–oxide–semiconductor process (only standard transistors with threshold voltage $V_{t} approx 0.4 hbox{V}$ were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.6 GHz at a low supply voltage of 0.65 V. The advantages of a high-impedance input, rail-to-rail output swing, robustness against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of $10^{-9}$ at 1.2-V supply, an amplitude at the input of 16.5 mV at 4 GHz has to be applied. If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is necessary. The power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V) and 128 $muhbox{W}$ at 0.6 GHz (0.65 V). Simulations show an offset standard deviation of about 6.1 mV at 0.65-V supply. With an on-chip measurement circuit, the delay time of the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V supply, is obtained.      

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

A Si bipolar 21-GHz/320-mW static frequency divider

A silicon bipolar divide-by-eight static frequency divider was developed. A state-of-the-art advanced borosilicate-glass self-aligned (A-BSA) transistor technology that has a cutoff frequency of 40 GHz at V_ce=1 V was applied. Optimum circuit and layout designs were carried out for high-speed/low-power operation. The single-ended input realized by an on-chip metal-insulator-metal (MIM) capacitor makes it easy to use in microwave applications. Ultrahigh-speed operation, up to 21 GHz, was realized, with 320-mW power dissipation from a single +5-V supply. The static frequency divider is a suitable prescaler for phase-locked oscillators (PLOs), completely covering microwave frequencies from L band through Ku band (1-18 GHz)     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

A 4.3-GHz VCO with 2-GHz tuning range and low phase noise

A voltage-controlled oscillator (VCO) based on double cross-coupled multivibrator structure with a center frequency of 4.3 GHz and a tuning range of 2 GHz has been designed and implemented in standard 0.35 μm BiCMOS technology. The measured phase noise is 113 dBc/Hz at 600-kHz offset frequency from the carrier. The VCO draws 14.6 mA from the 2.5-V supply     

Design and experiments on a high-resolution multi-gigahertzsampling rate superconducting A/D converter

Work towards a high-resolution multi-gigahertz sampling rate A/D converter is presented. A brief review of the overall architecture which consists of a coarse section and an interpolator section is given. Experiments on two designs for the coarse sections are discussed. One is a 6-bit A/D converter built with two-leaf phase tree periodic comparators. Asynchronous beat frequency tests at 2.01 GHz sampling rates indicate this circuit is capable of 6 bits of resolution at 2 GHz input bandwidth. The resolution falls off to about 5 bits at 4 GHz and 4 bits at 6 GHz. The other approach involves two related novel single threshold comparators with large dynamic range. For one of the comparators, dynamic range in excess of 60 db is demonstrated by transfer characteristic and input current noise measurements, while the other showed 54 db of dynamic range. A chain of 15 comparators based on one of the designs has been designed and tested. Asynchronous beat frequency tests at 2.01 GHz sampling rates show a monotonic response for input frequencies up to 8 GHz. Threshold offsets due to flux trapping limited the resolution in this set of experiments to about 5 bits. Experiments on a periodic interpolator circuit based on the two-leaf phase tree comparator are also presented. The results suggest that it should be possible to obtain 10-bits of resolution with this approach     

A Si bipolar 28-GHz dynamic frequency divider

A dynamic frequency divider applying the regenerative frequency division principle has been developed. A spiral inductor on the silicon substrate used as a load is characterized, and an improved one-port model with the substrate resistance is discussed. A 1/16 frequency divider was implemented with a silicon bipolar technology with a cutoff frequency of 40 GHz. The operation frequency range was 11.8-28.1 GHz, covering the Ka band (18-26.5 GHz). The inductive load has improved the maximum operation frequency by 7%, compared with a conventional circuit. Complemented with a 21-GHz static frequency divider previously reported by the authors, the whole microwave frequency range up to 26.5 GHz has been completely covered with the silicon bipolar technology. The maximum operation frequency of a silicon MMIC has been extended to the millimeter-wave frequency region for the first time