Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias $V_{rm bg}$, resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). $V_{rm bg}$ only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 $hbox{V}/muhbox{m}$ of the conventional SOI to 457 $hbox{V}/muhbox{m}$ at $V_{rm bg} = hbox{0 V}$, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO.      

The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET

In this letter, we investigate the effects of oxide traps induced by various silicon-on-insulator (SOI) thicknesses $({T}_{rm SOI})$ on the performance and reliability of a strained SOI MOSFET with SiN-capped contact etch stop layer (CESL). Compared to the thicker ${T}_{rm SOI}$ device, the thinner ${T}_{rm SOI}$ device with high-strain CESL possesses a higher interface trap $({N}_{rm it})$ density, leading to degradation in the device performance. On the other hand, however, the thicker ${T}_{rm SOI}$ device reveals inferior gate oxide reliability. From low-frequency noise analysis, we found that thicker ${T}_{rm SOI}$ has a higher bulk oxide trap $({N}_{rm BOT})$ density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior TDDB reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker ${T}_{rm SOI}$ devices in this strain technology.      

Design and Characterization of CMOS/SOI Image Sensors

The design, operation, and characterization of CMOS imagers implemented using: 1) "regular" CMOS wafers with a 0.5-mum CMOS analog process; 2) "regular" CMOS wafers with a 0.35-mum CMOS analog process; and 3) silicon-on-insulator (SOI) wafers in conjunction with a 0.35-mum CMOS analog process, are discussed in this paper. The performances of the studied imagers are compared in terms of quantum efficiency, dark current, and optical bandwidth. It is found that there is strong dependence of quantum efficiency of the photodiodes on the architecture of the image sensor. The results of this paper are useful for designing and modeling CMOS/SOI image sensors     

High $Q$ -Factor Microrings Using Slightly Etched Rib Waveguides

The paper reports the design, fabrication and characterization of silicon-on-insulator (SOI) microring resonators using shallow etched rib waveguides. The variation of the $Q$-factor of microring resonators as a function of the ring diameter and coupling gap between the input waveguide and the ring is studied. Such structures are fabricated using e-beam lithography and reactive ion etching steps. Propagation loss of shallow etching rib waveguide has been evaluated to 0.8 dB/cm for wavelengths around 1550 nm. With a ring diameter of 100 $mu{rm m}$ and a coupling gap of 450 nm, the measured $Q$ -factor is 35300. These results are matched by 3-D numerical optical modeling.      

Narrow-core hollow optical waveguide with nanostructured SOI as ultra-low loss platform for efficient photodetection

A nanostructured hollow optical waveguide based on high-index contrast grating (HCG) embedded SOI is proposed. An ultra-low propagation loss of 1.22 dB/m even at narrow, 1-\(\upmu \)m thick, air-core is reported. A high-performance photodetection is realized by the introduction of hollow core in form of intrinsic region in the photodetection (PIN) layer within HCG-assisted narrow-core waveguide. A sufficiently high responsivity of 0.8 A/W and quantum efficiency of 64% are obtained at 1550-nm which is possible because of the presence of surface modes within HCG which get coupled in the photodetection layer leading to a strong optical confinement in that layer. High reflectivity, small penetration length and coupling of lateral surface modes in HCG make it possible to offer improved waveguiding and hence photodetection.     

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the high-density oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to $hbox{6} times hbox{10}^{6} hbox{V/cm}$, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 $muhbox{m}$ and drift length of 15 $muhbox{m}$ on a thin SOI substrate.      

The Corbino Pseudo-MOSFET on SOI: Measurements, Model, and Applications

We propose the combination of magnetoresistance (MR) and Pseudo-MOSFET ($ Psi$-MOSFET) measurements as an improved method for the characterization of silicon-on-insulator (SOI) materials. Measurements were performed on ultrathin SOI $Psi$ -MOSFETs with Corbino geometry by applying high magnetic field and substrate biasing. Several models and extraction methods are developed and compared for an accurate evaluation of electron mobility. In particular, the series resistance effect is removed by using appropriate corrections. The MR mobility can be determined at low or variable electric field. The MR mobility behavior is investigated as a function of effective electric field, temperature, and film thickness. The correlation between the MR mobility and effective mobility, determined in $Psi$-MOSFETs at zero magnetic field, enables a detailed analysis of the electron transport and scattering mechanisms in the silicon thin film.      

Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-$ muhbox{m}$ three-dimensional (3-D)–SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D–SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D–SOI technology are also characterized and compared with conventional bulk CMOS technology.      

High Quality-Factor 1-D-Suspended Photonic Crystal/Photonic Wire Silicon Waveguide Micro-Cavities

We have successfully fabricated and characterized suspended one-dimensional (1-D) photonic crystal/photonic wire (PhC/PhW) waveguide micro-cavities based on silicon-on-insulator (SOI). Our experiments have shown an enhancement of the resonance ${Q}$ -factor from 18 700 to approximately 24 000, with normalized optical transmission of 70%, after removing the silica cladding underneath the silicon waveguide. We have also demonstrated that, for this condition, the resonance peak wavelength can be controlled by varying the length of the micro-cavity. These results were obtained by removing the silica cladding below the silicon waveguide to produce a “hanging” wire waveguide. The three-dimensional (3-D) finite-difference time domain (FDTD) simulation approach used shows good agreement with measured results.      

Performance characteristics of <Emphasis Type="Italic">p</Emphasis>-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

The length of Source/Drain (S/D) extension (L_SDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer L_SDEpFinFET provides a larger series resistance and degrades the drive current (I_DS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter L_SDE plus the shorter channel length demonstrates a higher trans-conductance (G _m ) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer L_SDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current.     

Silicon-on-insulator asymmetric optical switch based on total internal reflection

Based on the large cross-section single-mode rib waveguide condition, total internal reflection (TIR) and the plasma dispersion effect, a silicon-on-insulator (SOI) asymmetric optical waveguide switch with transverse injection structure has been proposed and fabricated, in which the SOI technique utilizes silicon and silicon dioxide thermal bonding and back-polishing. The device performance is measured at a wavelength of 1.3 /spl mu/m. It shows that the extinction ratio and insertion loss are less than -18.1 and 6.3 dB, respectively, at an injection current of 60 mA. Response time is 110 ns.     

A New Approach of Lateral RF MEMS Switch

This paper presents a novel lateral series microwave switch fabricated on a silicon-on-insulator (SOI) substrate with a finite ground coplanar waveguide (FGCPW) configuration which is laterally actuated by the electrostatic force. The switch is built with a cantilever beam in the direction of the signal line and a fixed electrode is located opposite the cantilever beam. The mechanical structures are fabricated using SOI deep reactive ion etching (DRIE) and shadow mask technology. The fabricated lateral RF MEMS switch has an isolation of 16 dB at 20 GHz. The insertion loss of the switch is 1 dB and return loss is 15 dB at 20 GHz. The threshold voltage is 19.2 V and switching time is 30 s.     

一种提高SOI电光开关消光比的优化设计

针对电流注入型SOI光开关在切换时难以克服的消光比变差的问题,提出了一种非对称的开关结构设计.然后依照实际器件的结构建立了SOI光开关的3D光学模型,对光开关中3D光场传输和输出光功率进行了模拟与分析.最后运用该模型对SOI光开关在电流切换时的消光比变化的问题进行了比较深入的研究,计算结果表明,提出的非对称的开关结构可以将SOI电光开关的消光比提高5 dB左右.     

Individually Addressable AlInGaN Micro-LED Arrays With CMOS Control and Subnanosecond Output Pulses

We report the fabrication and characterization of an ultraviolet (370 nm) emitting AlInGaN-based micro-light- emitting diode (micro-LED) array integrated with complementary metal–oxide–semiconductor control electronics. This configuration allows an 8 $times$ 8 array of micro-LED pixels, each of 72-$muhbox{m}$ diameter, to be individually addressed. The micro-LED pixels can be driven in direct current (dc), square wave, or pulsed operation, with linear feedback shift registers (LFSRs) allowing the output of the micro-LED pixels to mimic that of an optical data transmitter. We present the optical output power versus drive current characteristics of an individual pixel, which show a micro-LED output power of up to 570 $muhbox{W}$ in dc operation. Representative optical pulse trains demonstrating the micro-LEDs driven in square wave and LFSR modes, and controlled optical pulsewidths from 300 ps to 40 ns are also presented.      

A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18‐μm SOI CMOS Technology

This paper presents a 5‐bit digital step attenuator (DSA) using a commercial 0.18‐μm silicon‐on‐insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T‐type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than 2.5° and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is , including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC‐to‐20‐GHz SOI DSA.     

SOI光波导开关研究进展

SOI光波导是硅基光波导器件的基础,也是实现其它集成光学器件的基础。文章论述了SOI材料、SOI光波导以及SOI光波导开关的一些特性和研究进展。     

Promising CMOS ICs Based on Si/CaF2/Si Epitaxial Layers

It is shown that MBE-grown Si/CaF₂/Si heterostructures are promising for SOI technology. On the basis of these heterostructures, test MIS/SOI structures were created. The mean electron mobility in the top silicon layer was found to be 450–600 cm²/(V s). A test CMOS IC with a CoSi₂gate and a CaF₂gate dielectric was produced. The room-temperature ultimate speed of this structure was estimated (and measured) at a level of 1.5–2 GHz for a supply voltage of 3.0 V.     

SOI LDMOSFET with Up and Down Extended Stepped Drift Region

To increase the breakdown voltage and decrease the ON resistance, a silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in which the drift region extends to the up and down oxides in a step shape is proposed. This up and down extended stepped drift SOI (UDESD-SOI) structure demonstrates a modified lateral electric field distribution with additional peaks as well as a decrease of the usual peaks near the drain and gate. Two-dimensional (2D) simulations were used to compare the characteristics of the proposed UDESD-SOI structure with those of other structures, viz. down extended stepped drift SOI (DESD-SOI), up extended stepped drift SOI (UESD-SOI), and conventional SOI (C-SOI). Under the same conditions, the breakdown voltage of the UDESD-SOI structure was nearly 35%, 117%, and 318% higher compared with the DESD-SOI, UESD-SOI, and C-SOI structure, respectively. To determine the optimum parameters for the UDESD-SOI structure leading to the highest breakdown voltage, a comparative study was performed to investigate the effect of the doping concentration in the drift region, buried oxide (BOX) thickness, and thickness of up and down extended steps (T ₁ and T ₂, respectively). In addition, the drain current (ON resistance) of the UDESD-SOI structure was found to be 13%, 43%, and 229% higher (16%, 65%, and 257% lower) than the values for the DESD-SOI, UESD-SOI, and C-SOI structure, respectively.     

A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low-dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the $gm/gds$ ratio of the current sources can be achieved. A power supply rejection of $>,$22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80$~$ pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.25–5 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7$~$V and a clock frequency of 1.6 GHz.      

Near-Ballistic Unitraveling-Carrier Photodiode-Based V-band Optoelectronic Mixers With Low Upconversion Loss and High Operation Current Performance Under Optical IF Signal Injection

We demonstrate near-ballistic unitraveling-carrier photodiode (NBUTC-PD)-based V-band (50–75 GHz) optoelectronic (OE) mixers which can upconvert the V-band optical local-oscillator (LO) and intermediate-frequency (IF) signals. The optical LO and IF signals share a single erbium-doped optical fiber amplifier (EDFA) which means that the mixing performance of the device can be optimized by properly adjusting the ratio between the injected optical LO and IF power to the EDFA. The utilization of the strong nonlinearity of the ballistic transport of the electrons in the NBUTC-PD under a reverse bias regime means that our device achieves a low upconversion loss ( $-$6 dB) under a very high operating current (23 mA) in V-band (60 GHz). We are able to improve the operating current at the V-band over that previously reported for UTC-PD-based OE mixers. This is made possible by an increase in the optimum operating voltage from the near forward bias (0 V) to the reverse bias regime ($-$1.7 V).