多值逻辑函数与其变元的几种无关性的谱分析

多值逻辑函数与它们的变元之间有许多种特殊关系,单从它们的表达式是较难判断的。本文给出了多值逻辑函数与其变元无关和统计无关的一些充分必要条件;给出了多值逻辑函数与其某些变元代数无关(也称为退化)的一些条件和最大程度地退化一个函数的方法;指出了这些结果在实际中的应用。所有这些结果都是Chrestenson谱方法来研究的。     

Spectral analysis of some independences on multiple-valued logical functions on their variables

There are many kinds of special relationships between multiple-valued logical functions and their variables, and they are difficult to be judged from their expressions. In this paper, some sufficient and necessary conditions of the independence and statistical independence of multiple-valued logical functions on their variables are given. Some conditions of algebraic independence of multiple-valued logical functions on some of their variables and the way to degenerate a function to the greatest extent are proposed, and some applications of these results are indicated. All the results are studied by using Chrestenson spectral techniques.     

Introducing disjoint spectral translation in spectral multiple-valued logic design

A new form of expansion of multiple-valued logical functions in generalised Fourier series in terms of the Chrestenson functions is presented. It is shown that this expansion exhibits the property of `disjoint spectral translation? known in binary spectral logic design. This allows extending the possibility of low complexity realisation to a large class of multiple-valued logical functions.     

Using decision trees for the minimization of multiple-valued functions

This paper presents a simple procedure for the approximate minimization of multiple-valued functions using multiple-valued decision trees. The proposed procedure is compared with a near-absolute procedure, using for the test four-valued functions of four variables. The results show a great advantage for our procedure with respect to the CPU time needed.     

多值逻辑函数组构成置换的一个充要条件

本文给出了一组多值逻辑函数构成置换的一个充要条件。     

基于模代数的真值向量计算及其在多值逻辑综合中的应用

本文提出了由函数的真值向量计算Reed-Muller展式的简捷方法,由此可判定函数能否线性分解或部分线性分解。用典型例子演示了其在多值逻辑综合中的应用,结果表明该方法行之有效。     

时序险象基本判据

本文利用几个定义和限制,得到了一外部激励x,n个状态变量电位异步时序电路的任一状态的一般逻辑表达式特性方程.将此方程与状态表结合,导出了产生时序险象时的状态变量数和稳定状态数所满足的条件;给出了对时序险象研究特别有用的基本判定法则.     

环Zm上随机变量联合分布的一种分解式及其应用

本文给出了ｍ值随机变量联合分布的分解式,考察了一类ｍ值（ｍ为正整数,ｍ≥２）逻辑函数Ｃｈｒｅｓｔｅｎｓｏｎ谱的“分解式”,并据此分解式给出了相关免疫ｍ值逻辑函数的一些新的构造法。     

Design of a modulo p multiplier

Some basic problems on the design of multiple-valued circuits are discussed on the basis of a modulo 5 full-multiplier. It is shown that appropriate transformations at the highest abstraction level may reduce some design constraints. In the case of the mod 5 multiplier, it is possible to alleviate linear dynamics range demands. Moreover it is shown that multiple-valued design may offer some space-time trade-offs with respect to binary.     

CIRCUIT TESTABLE DESIGN AND UNIVERSAL TEST SETS FOR MULTIPLE-VALUED LOGIC FUNCTIONS

The circuit testable realizations of multiple-valued functions are studied in this letter. First of all, it is shown that one vector detects all skew faults in multiplication modulo circuits or in addition modulo circuits, and n＋1 vectors detect all skew faults in the circuit realization of multiplevalued functions with n inputs. Secondly, min（max） bridging fault test sets with n＋2 vectors are presented for the circuit realizations of multiple-valued logic functions. Finally, a tree structure is used instead of cascade structure to reduce the delay in the circuit realization, it is shown that three vectors are sufficient to detect all single stuck-at faults in the tree structure realization of multiplevalued logic functions.     

采用多输入浮栅MOS器件的四值编-译码电路设计

提出一种采用多输入浮栅MOS管设计具有可控阈值功能的电压型多值逻辑电路的方法.对每个浮栅MOS管的逻辑功能均采用传输开关运算予以表示以实现有效综合。在此基础上提出了一种新的电压型多输入浮栅MOS四值编码器和译码器设计。所提出的电路在结构上得到了非常明显的简化,并可采用标准的双层多晶硅CMOS工艺予以实现。此外,这些电路具有逻辑摆幅完整、延迟小等特点。采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性。     

Blind separation using convex functions

In this paper, the problem of how to conveniently estimate independence from observations is addressed. Random variables (RVs) are transformed by their respective distribution functions and quantized. Then, the uniformity of the joint probability of the obtained discrete RVs is evaluated using a strictly convex function. An infinite class of new independence measures, named quasientropy (QE), is thus proposed. Unbiased estimates of the values of the distribution functions at the observations are directly utilized in estimating QE. The linear instantaneous blind source separation (BSS) algorithm based on QE can separate signals with arbitrary continuous distributions.     

Novel multipeak current-voltage characteristics of series-connectednegative differential resistance devices

Three-peak current-voltage (I-V) characteristics can be obtained from the combination of two series-connected negative differential resistance (NDR) devices under certain conditions. We discuss these constraint conditions and demonstrate their role in the design of multipeak I-V characteristics based on NDR devices in series. These phenomena will provide some useful concepts in the multipeak circuit design. Especially, these novel multipeak I-V characteristics can be applied to the multiple-valued logic applications with less devices compared to the traditional structure that stacks N identical devices to obtain N peaks in the I-V curve     

Branch-exchange sequences for reconfiguration of lightwave networks

Some of today's telecommunications networks have the ability to superimpose some form of logical connectivity, or virtual topology, on top of the underlying physical infrastructure. According to the degree of independence between the logical connectivity and the physical topology, the network can dynamically adapt its virtual topology to track changing traffic conditions, and cope with failure of network equipment. This is particularly true for lightwave networks, where a logical connection diagram is achieved by assignment of transmitting and receiving wavelengths to the network stations that tap into, and communicate over, an infrastructure of fiber glass. Use of tunable transmitters and/or receivers allow the logical connectivity to be optimized to prevailing traffic conditions. With rearrangeability having thus emerged as a powerful network attribute, this paper discusses the reconfiguration phase which is the transition between the current logical connection diagram and a target diagram. We consider here an approach where the network reaches some target connectivity graph through a sequence of intermediate connection diagrams, so that two successive diagrams differ by a single branch-exchange operation. This is an attempt at logically reconfiguring the network in a way that is minimally disruptive to the traffic. We propose and compare three polynomial-time algorithms that search for “short” sequences of branch-exchange operations, so as to minimize the overall reconfiguration time. For networks made of up to 40 stations, theoretical and simulation results show that, when a randomly selected diagram is to be changed to another randomly chosen diagram, the average number of branch-exchange operations required grows linearly with the size of the network     

N维四阶Hadamard矩阵与H_4函数

本文定义了一类适于研究一般n维四阶Hadamard 矩阵的逻辑函数,即H_4函数,并借助于H_4函数,讨论了n维四阶Hadamard矩阵的性质,构造了某些计数问题,并且给出了几个等价判别条件。     

Stochastic and fuzzy logics

It is shown that it is possible to regard stochastic and fuzzy logics as being derived from two different constraints on a probability logic: statistical independence (stochastic) and logical implication (fuzzy). To contrast the merits of the two logics, some published data on a fuzzy-logic controller is reanalysed using stochastic logic and it is shown that no significant difference results in the control policy.     

A novel multiple-valued logic gate using resonant tunneling devices

We demonstrate a novel multiple-valued logic (MVL) gate using series-connected resonant tunneling devices. Logic operation is based on the control of the switching sequence of these devices through the modulation of their peak currents by the input signal. We obtain the literal function, one of fundamental MVL functions, by integrating three InGaAs-based resonant-tunneling diodes with two HEMT's on an InP substrate. The gate configuration is greatly simplified compared with a conventional literal gate employing CMOS circuits     

Ant colony optimisation–direct cover: a hybrid ant colony direct cover technique for multi-level synthesis of multiple-valued logic functions

The use of non-binary (multiple-valued) logic in the synthesis of digital systems can lead to savings in chip area. Advances in very large scale integration (VLSI) technology have enabled the successful implementation of multiple-valued logic (MVL) circuits. A number of heuristic algorithms for the synthesis of (near) minimal sum-of products (two-level) realisation of MVL functions have been reported in the literature. The direct cover (DC) technique is one such algorithm. The ant colony optimisation (ACO) algorithm is a meta-heuristic that uses constructive greediness to explore a large solution space in finding (near) optimal solutions. The ACO algorithm mimics the ant's behaviour in the real world in using the shortest path to reach food sources. We have previously introduced an ACO-based heuristic for the synthesis of two-level MVL functions. In this article, we introduce the ACO–DC hybrid technique for the synthesis of multi-level MVL functions. The basic idea is to use an ant to decompose a given MVL function into a number of levels and then synthesise each sub-function using a DC-based technique. The results obtained using the proposed approach are compared to those obtained using existing techniques reported in the literature. A benchmark set consisting of 50,000 randomly generated 2-variable 4-valued functions is used in the comparison. The results obtained using the proposed ACO–DC technique are shown to produce efficient realisation in terms of the average number of gates (as a measure of chip area) needed for the synthesis of a given MVL function.     

Dynamic-type CMOS four-valued logic circuits

We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given.     

功能险象的简化快速算法研究

文中利用参与逻辑函数和逻辑函数余式的理论,得到了一系列重要的规律,使用导出的等效二变量逻辑余式状态变化过程可对功能冒险精确定位,避免了繁琐沉重的计算,为数字电路和计算机设计奠定了基础。