宽带分数抽取数字下变频设计

在雷达宽带接收系统中,数字中频接收采样率的选择要受限于射频系统的整体设计架构,信号处理系统需要的基带信号数据率可能无法通过对采样信号进行整数抽取获得。针对宽带系统采样率高、数字下变频采用并行多相滤波算法结构、基带信号由多个并行支路组成的特点,以及FPGA处理速率的限制,宽带信号分数抽取运算通常只能采用并行多相方式实现。在宽带数字下变频并行多路基带信号的基础上,通过并行多相内插滤波和并行多相抽取滤波算法,不需要提高FPGA的处理时钟,实现对大带宽信号的分数抽取运算。     

改进的宽带信号有理数倍采样率变换结构

针对现有的数字器件无法满足对宽带信号进行有理数倍采样率变换的问题,提出了一种改进的宽带信号有理数倍采样率转换结构.在分析抽取器与内插器顺序的基础上,得出了等效变换的前提条件,并结合多相滤波结构使改进的结构更具有实际应用价值.仿真实验证明了改进后结构的有效性.通过与现有有理数倍采样率变换结构运算量对比分析表明,改进后的结构的运算效率为传统结构运算效率的1/(LM)倍,其中L和M为变换过程中的内插因子和抽取因子.     

宽带分数延时滤波器的优化设计及FPGA实现

提出了一种可变分数延时宽带数字滤波器的优化设计方法,该方法首先采用内插的方法提高采样率,降低信号的归一化带,再采用Farrow结构来实现分数延时,通过抽取,恢复信号的初始采样率.其实现形式采用基于多相滤波的级联结构,使得内插和抽取相互抵消,降低滤波器的阶数,提高运算效率.采用基于FPGA的并行分布式算法,设计利用了器件的结构特点以及与器件特性独立的2种方法,在时域实现了高速、高阶的宽带分数延时滤波器,并在Altera Stratix FPGA上进行了仿真验证,最高工作频率分别为184 MHz和119 MHz.     

基于频率响应屏蔽技术的采样率变换新结构

介绍了频率响应屏蔽(FRM)技术在采样率变换技术中的应用,分析了FRM的简化结构——内插滤波器的设计方法。将此滤波器应用于采样率变换中,并结合多相滤波思想提出了一种高效的FRM采样率变换结构,此结构能极大降低采样率变换实现复杂度。最后通过设计实例,验证了此结构的高效性。     

认知无线电中下变频信号处理的频谱研究

针对认知无线电中下变频处理中的信号抽取过程对信号频谱的影响进行了研究,信号抽取由积分梳状(CIC)滤波器、半带(HB)滤波器及多相滤波器级联而成,利用傅里叶变换对各环节处理后的信号频谱进行理论推导,得出各级抽取后信号频谱的变化规律及各参数选择要注意的问题。通过实验仿真,对整个抽取系统进行测试,仿真结果表明,采样率为fs的信号经过3级抽取,且抽取倍数为D_(CIC)·D_(HB)·D_(多相)时,输出信号的采样率变为fs/(D_(CIC)·D_(HB)·D_(多相)),与理论推导结果一致,实现了多速率信号处理。     

一种基于多相滤波的高速信号处理算法

在多速率信号处理中,常采用多相滤波结构以有效地降低系统的运算量,提高系统信号处理的实时性。如果采用内插系统的多相滤波结构,在实现过程中受系统时钟频率的约束,将无法实现采样率超过时钟频率的高速率信号的传输。提出了一种基于多相滤波结构的新型高速信号处理算法,对高速信号进行多级多相滤波,从而将信号进行多相分解,采用多通道传输;利用多路低采样率信号得到高采样率的输出信号,并在接收端进行信号合成。具有运算量小、消耗资源少、便于实现等优点,并通过公式推导及仿真结果验证了其正确性,解决了高速率信号受系统时钟频率限制难以实现的问题。     

多相滤波法和低通滤波法实现正交插值的比较

正交插值可以由低通滤波法和多相滤波法来实现,文中从实现方式、采样率、滤波器方面进行了比较,使用matlab对两种方法进行了仿真分析,并在分析的基础上分别使用Xilinx公司的Virtex4 FPGA实现了两种结构.通过比较得出,多相滤波法相对于低通滤波法有很多优点:结构简单、资源占用少且易于实现.     

基于FPGA的载波调制系统

线路调制单元是电力线载波机的关键部件之一.本文提出并实现了一种利用FPGA芯片完成线路调制的方案.在FPGA芯片中完成信号的正交变换,由FIR滤波器和CIC滤波器实现采样率的变化.通过与载波的相乘完成整个调制过程     

基于FPGA和SMT387的SAR数据采集与存储系统

为了解决现有的合成孔径雷达SAR回波信号采集存储系统不能同时满足高采样率、高采样精度、高存储速度、大存储容量、脱机运行的问题.该文提出了一种基于FPGA和DSP的SAR回波信号的采集与存储系统.该系统采用专用于数据硬盘存储的DSP功能模块SMT387和Virtex 4系列的 FPGA 器件XC4VFX12设计.Virtex 4系列FPGA主要控制采集存储系统的总体时序,采集回波信号的有效部分存入SATA硬盘,SMT387主要运用纽曼-皮尔逊准则的滑窗检测算法检测回波信号的具体位置,并计算出各种位置信息的具体参数,再将这些参数传到FPGA,控制系统的总体时序.该系统采样率达170百万次/秒,能够对正交两路信号同时采集,能够脱机、长时间存储120MB、16位的高速数据.     

基于FPGA的直流相位跟踪检测系统设计

提出了一种基于FPGA实现的直流相位跟踪检测系统,分析了系统输出信号与输入信号保持同步的实现原理,并建立了基于FPGA的设计模型,进行了硬件仿真,确定了系统的采样率,最后通过实验验证了此FPGA系统可实现相位实时检测,误差为0.2%,证明了此系统可满足干涉式光纤电压传感器对相位检测的性能要求.     

用HSP50214B实现跳频信号的实时变频解跳处理

本文提出了一种对跳频信号进行解跳的方法。其基本思想是利用数字变频将跳频信号不同频率的各个跳段信号变频到统一载频上,使其转变为定频信号。文中着重论述了变频方案和内部参数的设计,并通过具体的例子说明了本方法基于HSP50214B的实现。     

一种高速实时信号多相位分解滤波方法

本文提出了一种高速实时信号多相位分解滤波方法,讨论了多相位分解滤波的基本原理、设计及FPGA实现,给出了多相位分解滤波算法的实现方案。在现有FPGA器件上实现了多相位分解滤波算法,可满足信号实时处理需求。     

On the use of a digital computer as a two-phase variable-amplitudevariable-frequency oscillator

A feasibility study on the use of a digital computer as a variable-amplitude variable-frequency oscillator which generates two-phase sinusoidal excitation control signals for a dual-excited synchronous generator is described. The oscillator uses two input signals. One input signal is used to control the frequency of the oscillator outputs, and the other is used to control their amplitudes. By a single variable, the software can be configured to vary the oscillator frequency range and to greatly reduce (almost eliminate) the harmonic distortion of the output signals. The harmonic distortion is constant and independent of the output frequency for each possible oscillator frequency range. The software-based oscillator design is flexible and can be used to generate different types of multiphase signal waveforms     

A Single-Stage Direct Interpolation Multiphase Clock Generator with Phase Error Averaging

Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 m, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively.     

A Software Defined Radio Platform with Direct Conversion: SOPRANO

In this paper, a new software defined radio platform with direct conversionisintroduced.The platform is named SOPRANO, which stands for Software Programmableand Hardware Reconfigurable Architecture for Network.Main features of SOPRANO include a high-level design methodologyfor digital circuits, direct conversion based on six-port technology, andnovel digital signal processingalgorithms for multi-band and multi-mode operation.The first prototype of the SOPRANO platform has been built and was ableto receive M-ary PSK (Phase Shift Keying)and QAM (Quadrature Amplitude Modulation) signals,with two different carrier frequencies at 2.45 GHz and 5.25 GHz,by changing signal-processing software.     

Current-mode multiphase sinusoidal oscillator based on current differencing units

This paper describes the design and experimental verification of a current-mode multiphase sinusoidal oscillator (MSO) employing current differencing units. The oscillator, composed of n 1st-order all-pass sections, generates harmonic current signals with 2n equidistant phase shifts, where n ≥ 2. Compared with conventional MSOs, this circuit is characterized by an extremely simple circuitry and a minimum number of passive and active components. The oscillation condition and the frequency of oscillation are orthogonally controlled. The proposed circuit is suitable for IC fabrication. Experimental verification on an erlier manufactured chip together with a detailed analysis of real influences are included in the paper.     

A Grounded-Resistor Current Conveyor-Based Active-R Multiphase Sinusoidal Oscillator

A multiphase active-R sinusoidal oscillator circuit is presented.The oscillator can produce M signals (M being even or odd) equally spaced inphase. The circuit has low component count, uses grounded resistors andenjoys low active and passive sensitivities. The feasibility of convertingthe circuit into a voltage controlled multiphase oscillator is studied.Simulation results are included.     

双/多基地综合脉冲孔径地波雷达的信道化接收技术研究

双/多基地综合脉冲孔径地波雷达在发射站为多载频信号同时辐射,在接收站综合形成发射方向图之前需要对各发射信号分量进行分离.尽管采用数字混频和低通滤波器组可以对各发射分量进行分离,但运算量太大,难以实时实现.为此提出采用多相滤波器组信道化接收技术,设计该雷达的多相滤波器组信道化接收机.这种多相滤波器组信道化接收机与低通滤波器组信道化接收相比,运算量减少N²倍(N为信道数).最后给出了该雷达试验系统的实测数据处理结果,验证了这种多相滤波器组信道化接收技术在该雷达信号处理中的有效性.     

On the Realization of Multiphase Oscillators Using?Fractional-Order Allpass Filters

In this paper multiphase oscillators built using fractional-order allpass filters are presented. We examine the theory behind their operation and demonstrate their usefulness in the design of both multiphase and quadrature oscillators. Case design examples are given for various scenarios, while PSPICE and experimental results verify their operation     

多通道数字接收机的设计与实现

为了解决传统模拟中频接收机相位分辨率低等缺点,提出一种基于软件无线电的中频数字接收机技术。针对雷达信号的特点提出了脉宽匹配滤波器的设计方法。采用基于多相滤波的正交变换理论,以及基于脉宽匹配的数字滤波器方法完成了一种五通道中频数字接收机的设计。接收机利用五路高速A/D变换器对输入的模拟信号进行采样,然后将采样数据送入FPGA进行处理,最终完成了每两路信号相位差的提取。实验结果表明系统具有成本低、精度高、结构简单等特点,而且具有一定的工程应用价值。