中波碲镉汞/钝化层界面电学特性研究

HgCdTe表面/界面特性对器件性能具有重要的影响,表面/界面的状态主要依赖于表面处理和钝化工艺。采用Br2/CH3OH腐蚀液对液相外延(LPE)生长的中波HgCdTe薄膜进行表面处理后,使用Cd Te/Zn S复合钝化技术进行表面钝化,制备了相应的MIS器件并进行器件C-V测试。结果表明,HgCdTe/钝化层界面固定电荷极性为正,面密度为2.1×1011 cm-2,最低快界面态密度为1.43×1011 cm-2·e V-1,在10 V栅压极值下慢界面态密度为4.75×1011 cm-2,较低的快界面态密度体现出了CdTe/ZnS复合钝化技术的优越性。     

CdTe/ZnS复合钝化层对长波碲镉汞器件性能的影响研究

采用CdTe/ZnS复合钝化技术对长波HgCdTe薄膜进行表面钝化,并对钝化膜生长工艺进行了改进。采用不同钝化工艺分别制备了MIS器件和二极管器件,并进行了SEM、C-V和I-V表征分析,研究了HgCdTe/钝化层之间的界面特性及其对器件性能的影响。结果表明,钝化工艺改进后所生长的CdTe薄膜更为致密且无大的孔洞,CdTe/HgCdTe界面晶格结构有序度获得改善;采用改进的钝化工艺制备的MIS器件C-V测试曲线呈现高频特性,界面固定电荷面密度从改进前的1.671011 cm-2下降至5.691010 cm-2;采用常规钝化工艺制备的二极管器件在较高反向偏压下出现较大的表面沟道漏电流,新工艺制备的器件表面漏电现象获得了有效抑制。     

基于不同AlN钝化层的极性GaN MOS器件界面特性

界面质量是影响GaN MOS器件性能以及可靠性的主要因素之一,Al203栅介质与极性GaN界面间插入超薄非晶AlN作为钝化层可以有效改善GaN栅界面特性,针对AIN钝化层生长方式研究了GaN界面优化特性.通过GaN MOS电容的C-V和J-V特性,结合透射电子显微镜(TEM)表征分析,对比了不同生长条件的AlN插入层对GaN MOS电容的界面特性的影响.相比常规热生长AlN钝化层制备的样品,以等离子体NH3为N源在300℃下生长AlN钝化层制备的GaN MOS电容的频散和滞回特性均得到显著改善,界面态密度也略有改善.分析认为,经过等离子体NH3的轰击作用有效地抑制了GaN表面上Ga-O键的形成,在GaN表面直接生长AlN,从而改善了界面特性.     

HgCdTe阳极硫化+ZnS钝化膜表面与界面的研究

报道了HgCdTe阳极硫化+ZnS钝化膜表面与界面X射线光电子能谱(XPS)的研究及结果.系统地介绍了HgCdTe阳极硫化+ZnS钝化膜的制备,Br2-CH3OH与HgCdTe化学抛光的反应过程,阳极硫化的化学组成及生长机制.阐述了该钝化结构不同深度的组分分布及其对HgCdTe光伏器件电学特性的影响.     

Au/CdTe+ZnS/HgCdTe双层介质膜MIS器件的制备及研究

通过介质膜ZnS、CdTe薄膜材料的Ar+束溅射沉积研究,结合HgCdTe器件工艺,成功制备了以ZnS、CdTe双层介质膜为绝缘层的HgCdTeMIS器件;通过对器件的C-V特性实验分析,获得了CdTe/HgCdTe界面电学特性参数.实验表明溅射沉积介质膜CdTe+ZnS对HgCdTe的表面钝化已经可以满足HgCdTe红外焦平面器件表面钝化的各项要求.     

栅氧化层及界面电荷对SiC MOSFET阈值电压稳定性的影响

阈值电压不稳定是SiC MOSFET的一个主要问题，而栅氧化层及界面电荷是引起器件阈值电压不稳定的关键因素。结合三角波电压扫描法和中带电压法提取了SiC MOSFET中的栅氧化层陷阱电荷面密度、界面陷阱电荷面密度和可动电荷面密度随应力时间的变化量，总结了三种电荷面密度变化量在不同应力时间下的变化规律，分析了其对器件阈值电压不稳定性的影响，同时推测了长时间偏压作用下SiC MOSFET阈值电压稳定性的劣化机制。测试结果表明，栅氧化层陷阱电荷面密度、界面陷阱电荷面密度和可动电荷面密度在不同偏压温度下随应力时间的变化规律不同，常温应力下器件阈值电压稳定性劣化主要与栅氧化层陷阱电荷有关，而高温下，则主要与界面陷阱电荷有关。     

Au／CdTe＋ZnS／HgCdTe双层介质膜MIS器件的制备及研究

通过介质膜ZnS、CdTe薄膜材料的Ar^ 束溅射沉积研究,结合HgCdTe器件工艺,成功制备了以ZnS、CdTe双层介质膜为绝缘层的HgCdTe MIS器件;通过对器件的C－V特性实验分析,获得了CdTe/HgCdTe界面电学特性参数。实验表明：溅射沉积介质膜CdTe ZnS对HgCdTe的表面钝化已经可以满足HgCdTe红外焦麦面器件表面钝化的各项要求。     

HgCdTe MIS器件的制备及其界面电学特性的研究(下)

介绍了用高、低频组合电容法测量HgCdTe MIS器件钝化层界面态密度能量分布的基本原理和步骤．研究表明,自身阳极硫化 单层ZnS对HgCdTe的表面钝化已经达到光伏焦平面器件表面钝化的各项要求．     

长波碲镉汞材料阳极氧化膜/ZnS界面的电学特性参数

通过碲镉汞阳极氧化膜和磁控溅射ZnS膜,结合HgCdTe器件工艺,成功制备了以阳极氧化膜和磁控溅射ZnS双层钝化膜为绝缘层的“长波弱P”型HgCdTe MIS器件.通过对器件的C-V特性实验分析,获得了长波HgCdTe材料的阳极氧化膜/ZnS界面电学特性参数.并通过获得的界面参数,计算了阳极氧化和ZnS的双层钝化膜的表面复合速度.并对MIS器件的变温C-V特性进行了实验和分析.     

表面钝化对HfTiON栅介质Ge MOS电容性能的影响

通过NO、N2O对Ge衬底进行表面钝化,生长GeOxNy界面层,然后采用反应磁控共溅射方法制备HfTiN薄膜,并利用湿N2气氛退火,将HfTiN转化为HfTiON高κ栅介质.研究了表面钝化对MOS器件性能的影响,结果表明,湿NO表面钝化能改善界面质量,有效降低MOS电容的栅极漏电流,增强器件的可靠性.     

表面固定电荷对Hg1—xCdxTe光导探测器性能的影响

研究了表面固定电荷密度对ＨｇＣｄＴｅ光导探测器性能的影响，计算结果表明，表面固定电荷对器件的性能有着重要的影响，选择合适的钝化工艺，控制表面固定电荷密度，可以优化器件性能     

New surface treatment method for improving the interface characteristics of CdTe/Hg1−xCdxTe heterostructure

This paper presents a new simple method of HgCdTe surface treatment which consists of chemical oxidation of HgCdTe with nitric acid and removal of the oxide with ammonium hydroxide. The electrical properties of the electron-beam deposition CdTe passivation of Hg_0.7Cd_0.3Te are investigated with regard to the effects of HgCdTe surface etching, exposure to nitric acid, and the new surface treatment method. As the HgCdTe surface is progressively etched with bromine in methanol (Br-MeOH), the surface becomes rougher and a higher density of fixed charge is induced at the interface between CdTe and HgCdTe. Exposure to HNO₃ results in a very high density of fixed charge and performance degradation in metal insulator semiconductor (MIS) capacitors, which is due to the chemical oxide grown by HNO₃. The oxide growth rate is enhanced as the concentration of HNO₃ increases or as more H₂O is added. This oxide can be removed with NH₄OH. After the new surface treatment, MIS capacitors of Hg_0.7Cd_0.3Te show substantial improvement in electrical properties, such as low density of fixed charge and reduced hysteresis width, regardless of previous surface etching.     

HgCdTe-MISFET fabrication with multi-step surface passivation and quantum effects

We have used multi-step surface passivation process integrating electrochemical reduction and UV exposure with native sulfidization by H₂S gas to obtain high quality ZnS/p-HgCdTe interface. It shows very low parasitic interface charge density of the order of 10¹⁰cm⁻². The insulating ZnS layer also exhibits very high resistivity of ∼10¹² Θcm. The resulting fabricated HgCdTe-MISFETs show 2D quantum effects. Magnetoresistance measured at 1.5K displays oscillations which begin to appear above the gate voltage of 10V. They are identified as the Shubnikov-de Haas oscillations involving three electronic subbands. The magnetotransport data are quantitatively analyzed with the calculated Landau level-fan diagram and confirm the 2D subband quantization of the inversion layer at the ZnS/p-HgCdTe interface. This result demonstrates successful role of the multi-step surface passivation for realizing 2D ZnS/HgCdTe interface which will provide high quality 2DEG resevoir basis in future Hg-based narrow-gap nanostructure device applications.     

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.     

Metalorganic chemical vapor deposition CdTe passivation of HgCdTe

CdTe epilayers are grown by metalorganic chemical vapor deposition (MOCVD) on bulk HgCdTe crystals with x ~ 0.22 grown by the traveling heater method (THM). The THM HgCdTe substrates are (111) oriented and the CdTe is grown on the Te face. The metalorganic sources are DMCd and DETe, and the growth is performed at subatmospheric pressure. Ultraviolet (UV) photon-assisted hydrogen radicals pretreatment plays a dominant role in the electrical properties of the resulting heterostructures. The requirements of a good passivation for HgCdTe photodiodes vis-a-vis the passivation features of CdTe/HgCdTe heterostructures are discussed. The effect of valence band offset and interface charges on the band diagrams of p-isotype CdTe/HgCdTe heterostructures, for typical doping levels of the bulk HgCdTe substrates and the MOCVD grown CdTe, is presented. Electrical properties of the CdTe/HgCdTe passivation are determined by capacitance-voltage and current-voltage characteristics of metal-insulator-semiconductor test devices, where the MOCVD CdTe is the insulator. It is found that the HgCdTe surface is strongly inverted and the interface charge density is of the order of 10¹²cm² when the CdTe epilayer is grown without the UV pretreatment. With the in-situ UV photon-assisted hydrogen radicals pretreatment, the HgCdTe surface is accumulated and the interface charge density is -4. 10¹¹ cm^-2.     

紫外辐照对碲镉汞MIS结构复合特性的影响

用光电导衰退法和ＭＩＳ器件的电容－电压特性测量研究了紫外辐照对碲镉汞样品的影响。研究表明：紫外辐照使ＭＩＳ器件的氧化膜／碲镉汞界面固定电荷减少，表面由积累向平带变化；紫外辐照使碲镉汞样品的电阻明显增大，样品的表面复合速度上升，少子体寿命下降．说明紫外辐射不仅对碲镉汞样品的表面有影响，而且在磅镉汞体内也有影响，这些效应可以用碲镉汞表面能带结构的模型来解释。     

钝化处理对Al2O3/InP MOS电容界面特性的影响

制备了Al/Al_2O_3/InP金属氧化物半导体(MOS)电容,分别采用氮等离子体钝化工艺和硫钝化工艺处理InP表面。研究了在150、200和300 K温度下样品的界面特性和漏电特性。实验结果表明,硫钝化工艺能够有效地降低快界面态,在150 K下测试得到最小界面态密度为1.6×10¹⁰ cm^-2·eV^-1。与硫钝化工艺对比,随测试温度升高,氮等离子体钝化工艺可以有效减少边界陷阱,边界陷阱密度从1.1×10¹² cm^-2·V^-1降低至5.9×10¹¹ cm^-2·V^-1,同时减少了陷阱辅助隧穿电流。氮等离子体钝化工艺和硫钝化工艺分别在降低边界陷阱和快界面态方面有一定优势,为改善器件界面的可靠性提供了依据。     

A CdTe passivation process for long wavelength infrared HgCdTe photo-detectors

Passivant-Hg_1−xCd_xTe interface has been studied for the CdTe and anodic oxide (AO) passivants. The former passivation process yields five times lower surface recombination velocity than the latter process. Temperature dependence of surface recombination velocity of the CdTe/n-HgCdTe and AO/n-HgCdTe interface is analyzed. Activation energy of the surface traps for CdTe and AO-passivated wafers are estimated to be in the range of 7–10 meV. These levels are understood to be arising from Hg vacancies at the HgCdTe surface. Fixed charge density for CdTe/n-HgCdTe interface measured by CV technique is 5×10¹⁰ cm⁻², which is comparable to the epitaxially grown CdTe films. An order of magnitude improvement in responsivity and a factor of 4 increase in specific detectivity (D*) is achieved by CdTe passivation over AO passivation. This study has been conducted on photoconductive detectors to qualify the CdTe passivation process, with an ultimate aim to use it for the passivation of p-on-n and n-on-p HgCdTe photodiodes.     

Compositionally graded interface for passivation of HgCdTe photodiodes

A compositionally graded CdTe-Hg_1−xCd_xTe interface was created by deposition of CdTe on p-HgCdTe and subsequent annealing. The compositionally graded layer between CdTe and HgCdTe was formed by an interdiffusion process and was used for passivation. The composition gradient (Δx) in the interfacial region and the width of the graded region were tailored by adopting a suitable annealing procedure. The effect of process conditions on the interfacial profile and photoelectric properties such as lifetime and surface recombination velocity was studied in detail. Surface recombination velocity of the p-HgCdTe could be reduced to the level of 3,000 cm/s at 77 K, which represents very good passivation characteristics. The passivation layer formed by this method can be used for the fabrication of high performance and stable modern infrared detectors. Thus, a passivation process is developed, which is simple, effective, reproducible, and compatible with the HgCdTe device fabrication and packaging processes.