Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p/sup -/silicon substrates

A 900-MHz single-pole double-throw (SPDT) switch with an insertion loss of 0.5 dB and a 2.4-GHz SPDT switch with an insertion loss of 0.8 dB were implemented using 3.3-V 0.35-/spl mu/m NMOS transistors in a 0.18-/spl mu/m bulk CMOS process utilizing 20-/spl Omega//spl middot/cm p/sup -/ substrates. Impedance transformation was used to reduce the source and load impedances seen by the switch to increase the power handling capability. SPDT switches with 30-/spl Omega/ impedance transformation networks exhibit 0.97-dB insertion loss and 24.3-dBm output P/sub 1dB/ when tuned for 900-MHz operation, and 1.10-dB insertion loss and 20.6-dBm output P/sub 1dB/ when tuned for 2.4-GHz operation. The 2.4-GHz switch is the first bulk CMOS switch which can be used for 802.11b wireless local area network applications.     

Signal generation, control, and frequency conversion AlGaN/GaN HEMT MMICs

We review the design and experimental results of three new AlGaN/GaN high electron-mobility transistor monolithic microwave integrated circuits: a voltage-controlled oscillator (VCO), a single-pole-double-throw switch (SPDT), and a resistive field-effect transistor mixer. The VCO exhibits frequency range between 8.5-9.5 GHz with maximum output power of 35 dBm (at V/sub ds/=30 V) across a 50-/spl Omega/ load. The L/S band SPDT switch at 0.9, 1.8, and 2.1 GHz was measured to have 0.87-, 0.96-, 1-dB insertion loss and 46-, 42-, and 41-dB isolation, respectively. The switch also shows linear performance for the power levels up to 1 W in the insertion mode. A singly ended X-band resistive mixer has exhibited very low intermodulation, less than -60 dBc for the second and third harmonics of the IF at the RF power level of 10 dBm, and high power handling, P/sub 1 dB/ is estimated to be at least 1 W, with the conversion loss of 17 dB.     

$Ka$-Band Low-Loss and High-Isolation Switch Design in 0.13-$mu{hbox {m}}$ CMOS

This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P₁) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.     

An optoelectronic switching matrix with high isolation

A high-isolation (60 dB) 10×10 optoelectronic switch matrix with surface-depleted photoconductive crosspoints is reported. The device is designed for a bandwidth greater than 1 GHz and an isolation level greater than 60 dB. Ten 1.8-GHz channels are supported with 0-dB insertion loss and >125 dB/Hz dynamic range. The novel crosspoints require reliability improvement because they are unstable     

A 90-dB Microstrip Switch on a Plastic Substrate (Correspondence)

A single-pole double-throw (SPDT) microstrip switch has been designed on a plastic (polyolefin) substrate to switch two 10-W CW carriers into a common load over the frequency range 1.7 to 2.3 GHz. No tuning adjustments are used over this 30-percent bandwidth to obtain a 90-dB minimum isolation, a 23-dB minimum return loss, and a 1-dB maximum insertion loss. Units now in production typically have a 0.6-dB insertion loss, a 26-dB return loss, and isolation levels of 105/spl plus mn/5 dB.     

A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps<4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5×0.95 mm².     

A high-performance 40-85 GHz MMIC SPDT switch using FET-integrated transmission line structure

A compact ultra-broadband distributed SPDT switch has been developed using GaAs PHEMTs. An FET-integrated transmission line structure, where the source pad of the shunt FET has been integrated into the signal line while the drain has been grounded to a via-hole with minimum parasitic inductance, has been proposed to extend the operating bandwidth of the distributed switches. SPDT and SPST switches using this structure have been fabricated using a commercial GaAs PHEMT foundry. The SPDT switch showed low insertion loss (<2 dB) and good isolation (>30 dB) over an octave bandwidth from 40 to 85 GHz. At 77 GHz, the SPDT switch showed extremely low insertion loss of 1.4 dB and high isolation of 38 dB. The chip size was as small as 1.45/spl times/1.0 mm/sup 2/. To the best of our knowledge, this is among the best performance ever reported for an octave-band SPDT switch at this frequency range. SPST switch also showed the excellent performance with the insertion loss of 0.4 dB and isolation of 34 dB at 60 GHz.     

W波段单刀双掷开关

实现了一种采用微波开关（PIN）二极管设计的低插损、高隔离度的 W波段单刀双掷开关（SPDT）。电路采用了改进的 Y 型结和梳状线高通滤波器形式的鳍线结构,有效提高了端口隔离度,降低了插入损耗。仿真结果显示,导通端口在88 GHz～99 GHz内的插入损耗小于0.7 dB,断开端口隔离度大于58 dB。测试结果显示,在频段90 GHz～95 GHz内,输入端口与输出端口1之间的插入损耗低于3.7 dB、隔离度高于33 dB;输入端口与输出端口2之间的隔离度高于33 dB、插入损耗低于3.8 dB。     

带GaAs TTL电平驱动器的SPDT开关的模拟和性能

介绍了一种带ＧａＡｓＴＴＬ电平驱动器及单刀双掷（ＳＰＤＴ）开关的设计、模拟和测试结果。驱动器的设计采用了开关输入稳压负载,建立了所用器件的大信号模型,对电路进行了模拟分析和优化,模拟和测试结果吻合较好,开关时间达到５ｎｓ,插入损耗小于１．０ｄＢ,隔离度大于６０ｄＢ。     

GaAs PIN二极管大功率毫米波单刀双掷开关单片

采用76.2mm(3英寸)GaAs PIN二极管工艺设计和制作了大功率毫米波单刀双掷开关单片。采用并联结构的单刀双掷开关以获得较高的功率特性。在片测试表明,在30～36GHz工作频段,开关导通支路插损1.0dB,驻波优于1.5,开关关断端口隔离度大于34dB。开关在导通态下输入功率0.5dB压缩点P-0.5 dB大于5W。     

60-GHz-band coplanar MMIC active filters

This paper presents the design and performance of 60-GHz-band coplanar monolithic microwave integrated circuit (MMIC) active filters. To compensate for the loss of the passive filter, a resonator composed of a quarter-wavelength line is terminated by a circuit with a constant negative resistance over a wide frequency band. Cross-coupling is introduced to make the attenuation poles on both sides of the passband. We develop two types of two-stage filter: one with medium bandwidth and the other with narrow bandwidth. The former shows an insertion loss of 3.0 dB with a 3-dB bandwidth of 2.6 GHz and a rejection of larger than 20 dB at a 3-GHz separation from a center frequency of 65.0 GHz. This filter also shows a noise figure of 10.5 dB. The latter filter shows an insertion loss of 2.8 dB with a 10-dB bandwidth of 2.1 GHz at a center frequency of 65.0 GHz. It also shows an output power of 5.0 dBm at a 1-dB compression point. The loss variation due to temperature variation is successfully compensated using a gate bias control circuit. The size of the MMIC filters is 2.5 mm/spl times/1.1 mm.     

CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency

This paper presents the comprehensive considerations of CMOS transmit/receive (T/R) switch design towards ultra-wideband and over 15-GHz frequencies. Techniques for minimizing parasitics and increasing linearity are discussed. A customized transistor layout is proposed for T/R switch design and its effects on insertion loss and isolation are studied. The analysis shows that a series-only architecture using the customized transistor layout achieves better insertion loss and reasonable isolation. A double-well body-floating technique is proposed and its effects are discussed. A differential switch architecture without shunt arms is designed and verified by experimental results. Fabricated in 0.13-mum triple-well CMOS, the T/R switch exhibits less than 2 dB insertion loss and higher than 21 dB isolation up to 20 GHz. With resistive body floating and differential architecture, the high linearity is of ultra-wideband characteristic, more than 30-dBm power 1-dB compression point (P_1dB) is obtained up to 20 GHz in only 0.03 mm² active die area     

一种L～E波段的混合型射频MEMS单刀双掷开关设计

针对传统RF MEMS单刀双掷(SPDT)开关应用存在频段低、插入损耗高、隔离度低等问题,设计了一种混合型SPDT开关,通过在一条通路上设置接触式开关和电容式开关,实现了在L～E频段下的低插入损耗和高隔离度。通过设计蛇形上电极结构,降低了上电极的弹性系数,进而降低开关上电极下拉所需的驱动电压。采用HFSS仿真软件对混合型SPDT开关的射频性能参数进行了优化,并利用COMSOL对开关的蛇形上电极进行应力-位移分析。仿真结果表明,在DC～90 GHz的频段下,SPDT开关的插入损耗小于1.5 dB@90 GHz,隔离度大于52 dB@67 GHz、29 dB@90 GHz。此开关适用于无线通信系统、雷达系统和仪器测量系统等对工作频段要求高的领域内。     

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.     

A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells

A 31.3-dBm 900-MHz bulk CMOS T/R switch with transmit (TX) and receive (RX) insertion losses of 0.5 and 1.0 dB and isolation of 29 dB is demonstrated. The switch utilizes a floating-body technique, feed-forward capacitors, and 3-stack 3.3-V MOSFETs with 0.26-mum sub-design-rule (SDR) channel length. Using these, a 28-dBm 2.4-GHz T/R switch with TX and RX insertion losses of 0.8 and 1.2 dB, and isolation of 24 dB is also demonstrated. The power handling capability is limited by an abrupt output power drop before reaching the normal 1-dB compression point. The circuits are implemented in the UMC 130-nm mixed-mode triple-well CMOS process.     

Electronically switchable and tunable coplanar waveguide-slotlineband-pass filters

A coplanar waveguide (CPW)-slotline bandpass filter is described. The circuit allows planar integration of active and passive semiconductor devices both in series and in shunt. A microstrip-to-slotline transition designed to test the filter is also described. Two of the transitions exhibit an insertion loss of less than 1.0 dB over the 2.0-4.0-GHz range. A three-section CPW-slotline bandpass filter demonstrates an insertion loss of less than 0.2 dB over the passband centered at 2.9 GHz. A three-section CPW-slotline switchable bandpass filter integrated with three p-i-n diodes is discussed. It has a 0.7-dB insertion loss in the passband when the p-i-n diodes are off and a 25.0-dB isolation across the entire band when the p-i-n diodes are on. A three-section CPW-slotline varactor-tunable filter integrated with three varactor diodes is presented, showing a 2.0-dB insertion loss and over 20% electronic tuning range. Simple transmission line circuit models are used to optimize the design     

Low-power InP-HEMT switch ICs integrating miniaturized 2/spl times/2 switches for 10-Gb/s systems

This paper presents a wideband cold-FET switch with virtually zero power dissipation. The use of InP HEMTs with a low R/sub on//spl middot/C/sub off/ product enables us to configure a DC-to-over-10-GHz single-pole double-throw (SPDT) switch without using a shunt FET. The series-FET configuration offers a logic-level-independent interface and makes possible positive control voltage operation in spite of using depletion-mode FETs. A miniaturized 2/spl times/2 switch using two SPDT switches yields an insertion loss of less than 1.16 dB and isolation of more than 21.2 dB below 10 GHz, which allows us to increase the scale of the switch in a single chip easily. The add-drop operation combining two 2/spl times/2 switches in a single chip and a 4/spl times/4 switch IC integrating four 2/spl times/2 switches are presented. The packaged ICs achieve error-free operation up to 12.5 Gb/s with either positive or negative logic-level input. Extremely fast switching of /spl sim/140 ps is also successfully demonstrated.     

5.8-GHz CMOS T/R switches with high and low substrate resistances in a 0.18-/spl mu/m CMOS process

Two single-pole, double-throw transmit/receive switches were designed and fabricated with different substrate resistances using a 0.18-/spl mu/m p/sup $/substrate CMOS process. The switch with low substrate resistances exhibits 0.8-dB insertion loss and 17-dBm P/sub 1dB/ at 5.825 GHz, whereas the switch with high substrate resistances has 1-dB insertion loss and 18-dBm P/sub 1dB/. These results suggest that the optimal insertion loss can be achieved with low substrate resistances and 5.8-GHz T/R switches with excellent insertion loss and reasonable power handling capability can be implemented in a 0.18-/spl mu/m CMOS process.     

A DESIGN OF 0.25μm CMOS SWITCH

Single-Pole Double-Throw （SPDT） broadband switch has been designed in a 0.25gm Complementary Metal Oxide Semiconductor （CMOS） process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances （GSR） on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC （Direct Current） to 1GHz exhibits 55dB and insertion loss lower than 2.1 dB.     

单片集成GaAs MESFET微波开关——Ⅱ、宽带单刀单掷和单刀双掷开关电路

本文介绍了单片集成GaAs MESFET微波开关的设计方法和制作工艺.利用空气桥和通孔接地等工艺技术,研制成的调配型宽带单刀单掷开关在0.01～7GHz内,插损为2～3.5dB,隔离度不小于32dB;分布型宽带单刀双掷开关在4.5～7GHz内,插损为1～2dB,隔离度不小于21dB,5GHz下的最大功率容量为3瓦.实验也证实电路的开通时间小于0.6ns.