基于DSP+FPGA的高速数字信号处理平台

本文介绍了一种高速数字信号处理平台的实现方案,主要是基于FPGA DSP的结构来实现高速数字信号处理.该方案采用先进的FPGA和DSP芯片,借鉴了软件无线电的思想,通过DSP芯片对FPGA芯片的动态配置来实现具有通用性、可扩充性的硬件平台,并对其硬件结构和软件工作流程进行了阐述.     

可重构软件无线电射频系统设计

基于软件无线电通信设备对射频系统的要求，讨论了现阶段软件无线电设备主要采用的射频架构，并重点对射频系统中的工作频段、信道线性度、信道换频时间和信道带宽等关键参数的可重构方案进行了分析和设计。可重构方案提升了软件无线电射频系统的通用性、开放性和可扩展性。     

基于DSP和FPGA的数字化中频处理平台

本文介绍了一种基于软件无线电技术的数字化中频处理平台．谊平台以宽带A/D器件、高速FPGA、高速DSP为基础，以软件为核心．具有很好的通用性、灵活性和可兼容性。     

基于总线灵活配置FPGA设计

基于软件无线电的通信系统需要灵活可变的数据配置方案,传统的数据加载模式在实际应用中受到很多限制。文章在对FPGA的配置比特流文件进行了结构分析的基础上,提出了一种采用SlaveSerial模式通过系统PCI总线对FPGA进行数据配置的方法。     

基于CCD传感器的空间目标探测可重构高速图像处理机设计

针对CCD空间目标探测系统中图像数据量大、待检测目标信噪比低、实时性要求高等特点,提出了一种基于时空域融合滤波的运动弱小目标检测算法,并完成了一种基于FPGA和DSP的高速图像处理机设计.该设计充分利用FPGA灵活、可编程特性和DSP在实现复杂运算方面的高速、程序动态可加载特性,并结合流水、并行等具体实现方法,使得该结构具有高速、灵活和可重构等特点.实际应用表明该处理机设计能够有效满足空间目标CCD探测系统要求.     

一种可重构配置技术在软件无线电中的应用

提出了一种PowerPC和FPGA可重构配置技术,并以此构建了软件无线电系统,主要研究了系统的可重构软硬件设计方案。重点阐述了系统可重构实现的几个关键技术:可重构硬件核心架构构建,PowerPC重构配置软件构建,FPGA重构配置软件构建,并对系统的重构配置进行了试验测试。通过试验表明,该系统重构配置的成功率高、速度快,满足设计要求。     

基于DSP和FPGA的信号处理平台

本文介绍了一种基于DSP和FPGA高速数字信号处理平台的实现方案，重点研究了试验平台的硬件实现结构软件实现结构以及不同模式之间的切换充分体现了软件无线电系统的灵活性．开放性和兼容性的特点。     

基于FPGA的软件无线电调制器设计与实现

针对数字基带信号的特点和通信系统中对数字信号传输的要求,研究一种基于FPGA的DSP技术和DDS技术的软件无线电调制器的设计方法。在FPGA平台上设计具有ASK,FSK,PSK和QAM调制功能的软件无线电调制器。该系统具有可重复编程和动态重构的优点,使系统易于修改和功能升级,灵活性强。     

基于FPGA的高速误码仪接收端设计方案的探讨

基于FPGA(现场可编程门阵列)的高速误码仪相对于传统的误码仪的优点是:基于FPGA芯片,在硬件平台固定的情况下,可对软件方案进行灵活修改以实现不同的功能;可利用FPGA芯片的高速处理能力实现高速数据流的误码率测试。文中介绍了高速误码仪接收端的主要功能和接口,重点介绍了2种基于FPGA的高速误码仪接收端的设计方案,并比较了2种方案的优缺点。     

一种实用的通信硬件平台

基于软件无线电的思想,构建了一种实现软件无线电的平台。该平台采用了一种基于直接数字合成技术的器件AD9852,并且采用FPGA来控制实现。该平台具有结构简单、精度高的特点,是一种比较通用的数字系统模型。Matlab工具下的仿真研究证实,该模型是一种有效的实现软件无线电的方案。     

基于软件无线电的伪卫星接收机的设计与实现

提出了基于软件无线电的伪卫星接收机的数学模型和数字平台实现的两种方案：DDC＋DSP方案和FPGA＋DSP方案。通过对这两种方案的比较，得出在伪卫星接收机数字平台的设计中应采用FPGA＋DSP方案。     

An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

The channelizer in a software defined radio (SDR) base station extracts individual radio channels from the digitized wideband input signal at a very high sampling rate. The base station channelizer must be able to simultaneously extract multiple channels of non-uniform bandwidths corresponding to channel bandwidths of different communication standards. Reconfigurability and low complexity are the two key requirements in the SDR channelizer. A new reconfigurable filter bank (FB) architecture based on interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB can be used for obtaining very narrow passband channels with extremely low complexity. Using a cascaded structure of the proposed FB, it is possible to extract channels of fractional passband widths by changing the interpolation factor. Design example shows that the proposed FB offers complexity reduction of 84% over the conventional per-channel (PC) approach. The proposed FB has been implemented and tested on Xilinx Virtex 2v3000ff1152-4 FPGA. Implementation results show that the proposed FB offers area reduction of 48.37%, speed improvement of 52.7% and power reduction of 75.9% over the PC approach.     

基于SCA的软件无线电在FPGA上设计与实现

在分析现有基于SCA的软件无线电在FPGA上实现方案优缺点的基础上,提出了一种基于FPGA的CORBA通信系统设计方案,有效克服了原有实现方案的缺点,不但为FPGA上的波形组件提供了良好的可重用性、可移植性和动态部分重配置的支持,而且还有效提高了FPGA硬件资源的使用效率,降低了通用处理器的工作负担。最后,针对该设计方案搭建了硬件平台,并给出了系统的性能测试结果,测试结果表明此设计方案是行之有效的。     

FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System

Based on software defined radio (SDR) architecture, this paper develops a reconfigurable CORDIC vectoring module (CVM) and CORDIC rotation module (CRM) in FPGA to implement the carrier frequency offset (CFO) estimation and compensation circuits of an orthogonal frequency division multiplexing (OFDM) system. The experimental results show that the proposed SDR-pipelined architecture can save power and hardware resource compared with conventional pipelined architecture, because the designed CVM and CRM modules can be reused in the processing modules of CFO estimation and compensation circuit. The performance trade-off for CVM and CRM implemented with different quantized float number in FPGA is presented. Furthermore, the hardware reconfiguration function of CVM and CRM is also validated.     

智能天线技术及应用研究评述

智能天线是提高无线传输性能的一项关键技术,是无线通信领域持续的研究热点之一,其中部分研究成果已经在无线通信、雷达、电子对抗等广泛的领域获得了成功的应用,并且未来无线系统设计中会越来越多的采用智能天线技术.为此,文章首先简要回顾了有关智能天线技术的发展历史,介绍了其中主要的阵列处理算法原理,给出了基于软件无线电和FPGA/DSP等可重配置软硬件系统设计参考方案,通过一些设计实例分析了应用中的实际问题和解决途径,最后提出了有关这一技术领域未来发展的展望.     

A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupancy of 46%, due to the efficient resources reuse.     

Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design.     

Analysis and implementation of six-port software-defined radio receiver platform

With recent advances in semiconductor processing technology and the development of reconfigurable devices, high bit-rate software-defined radio (SDR) has become practical for commercial applications. This paper proposes an SDR receiver platform based on a new substrate integrated waveguide six-port structure. This SDR receiver platform operates from 22 to 26 GHz and it is designed to be robust, low cost, and suitable for different communication schemes. In this study, the receiver is demonstrated to support quadrature phase-shift keying and 16 quadrature amplitude modulation schemes. System-level simulation is made and prototype circuits are fabricated to evaluate the system performance. It is found that the combination of SDR and six-port technology can provide a great flexibility in system configuration, a significant reduction in system development cost, and also a high potential for software reuse. The proposed receiver shows a possible application of universal direct demodulator for future SDR terminals in various wireless communication systems.     

基于动态频谱接入的应急移动通信系统

新兴的动态频谱接入(DSA)技术可以解决频谱稀缺问题.本文在研究荷兰典型的下一代应急网络xGEN的基础上,分析了DSA在应急通信网络中的应用需求,设计了分级混合网络架构的DSA应急移动专用通信网络及其基于软件无线电(SDR)平台的快速可重配置的应急终端结构,并探讨了DSA设备特有的动态频谱管理功能实现的关键技术.     

SDR中新型自适应复分接芯片的板级验证

针对多用户型软件无线电(SDR)的发展需求,基于FPGA,采用新型时钟提取方案,设计实现了自适应数字复分接芯片的板级验证平台,详细阐述了平台的软、硬件设计及自适应实现过程,给出了平台的各项测试指标.测试结果表明,该平台可满足数字复分接芯片的验证需求.