Fuzzy thermal modeling for MCM placement

This paper introduces a fuzzy analytical model for the optimal component placement of the power dissipating chips on a multichip module substrate. Our methodology considers multiobjective component placement based on thermal reliability as well as routing length criteria. The objective of the coupled placement methodology is to enhance the performance and reliability of the multichip module system by obtaining an optimal cost during multichip module placement. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated using the finite element method.     

Reliability and wireability optimizations for chip placement on multichip modules

The chip placement problem of multichip module (MCM) designs is to map the chips properly to the chip sites on the MCM substrate. Chip placement affects not only the thermal characteristics of an MCM but also routing efficiency, which translates directly into manufacturability, performance, and cost. This paper presents a solution methodology for the optimal placement problem considering both thermal and routing design objectives simultaneously. The coupling is achieved through use of a hybrid-force model that is a combination of the traditional interconnection-force model and a novel thermal-force model. The placement procedure can be used as a design tool to place chips and then determine the tradeoffs which can be made in placing for reliability and wireability. Experiments on five examples including three benchmarks show that the present algorithm yields very high-quality results.     

Thermal analysis for indirect liquid cooled multichip module using computational fluid dynamic simulation and response surface methodology

This paper demonstrates the application of computational fluid dynamic (CFD) simulation and response surface methodology (RSM) in analyzing the thermal performance of a high input/outputs, seven chips, indirect liquid cooled multichip module which will be applied in a kind of supercomputer. A series of similar experiments and corresponding CFD simulations are conducted firstly to evaluate the validity of CFD simulation method and determine the interfacial thermal resistance of thermal grease iteratively, and then a three-dimensional CFD model is established to investigate the heat transfer and fluid flow of the multichip module. Based on the CFD model, the individual effects of factors such as thermal conductivity of the thermal interface material and thermal grease, thickness of the chips, space between chips, solder bump patterns, solder ball patterns, flow velocity and liquid inlet temperature on the thermal performance of the module are studied with one-factor-at-a-time experimentation, and after that, four significant factors are selected to establish a response surface model of the maximum temperature of the module with central composite design based RSM and analysis of variance.     

Evaluation of Thermal Resistance Matrix Method for an Embedded Power Electronic Module

Thermal characterization provides data on the thermal performance of electronic components under given cooling conditions. The most common thermal characterization parameter used to characterize the behavior of electronic components is the thermal resistance. In this work, experiments are conducted to obtain thermal characterization data for different chips in a multichip package. Using this data, it is shown that the assumption of a linear temperature rise with input power is valid within the expected range of operation of the electronic module. Secondly, the applicability of a resistance matrix superposition methodology to the packaging structure of an integrated power electronic module is evaluated. The temperatures and the associated uncertainties involved in using the resistance matrix superposition method are compared to those obtained directly by powering all chips. It is shown that for any arbitrary power losses from the chips, the resistance matrix superposition method can predict the temperatures of a multichip package with reasonable accuracy for temperature rise up to 50degC.     

Temperature measurements and thermal modeling of high power IGBT multichip modules for reliability investigations in traction applications

To study the failure mechanisms induced on high power IGBT multichip modules by thermal cycling stress in traction environment, a good knowledge of the temperature distribution and variations on the chips and in the interfaces between the different layers of the packaging is necessary. This paper presents a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits. The results of static and dynamic thermal simulation of a 1200A–3300V IGBT module are given and compared with the contact temperature measurements results. The investigation has been done within the RAPSDRA (Reliability of Advanced High Power Semiconductor Device for Traction Applications) European project.     

基于热叠加模型的叠层3D多芯片组件芯片热布局优化研究

 叠层三维多芯片组件(3D Multi-Chip Module,MCM)芯片的位置布局直接影响其内部温度场分布,进而影响其可靠性.本文研究了叠层3D-MCM内芯片热布局优化问题,目标是降低芯片最高温度、平均芯片温度场.基于热叠加模型并结合热传导公式,选取芯片的温度作为评价指标,确定出用于3D-MCM热布局优化的适应度函数,采用遗传算法对芯片热布局进行优化,得出了最优芯片热布局方案,总结出了可用于指导叠层3D-MCM芯片热布局设计的热布局规则;采用有限元仿真方法,对所得的热布局优化结果进行验证,结果表明热布局优化结果与仿真实验结果一致,本文所提出的基于热叠加模型的MCM热布局优化算法可实现叠层3D-MCM芯片的热布局优化.     

Multidisciplinary heat generating logic block placement optimization using genetic algorithm

A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using a genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared to the case in which only the wiring length is minimized.     

多芯片组件散热的三维有限元分析

基于有限元法的数值模拟技术是多芯片组件(Multichip Module)热设计的重要工具。采用有限元软件ANSYS建立了一种用于某种特殊场合的MCM的三维热模型,对空气自然对流情况下,MCM模型的温度分布和散热状况进行了模拟计算。并定量分析了空气强迫对流和热沉两种热增强手段对MCM模型温度分布和散热状况的影响。研究结果为MCM的热设计提供了重要的理论依据。     

A CMOS mainframe processor with 0.5-μm channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability     

Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance

The layout of power multichip modules is one of the key points of a module design, especially for high power densities, where couplings are enlarged. This paper focuses on dynamic current imbalance between paralleled chips. It can be principally attributed to gate circuit dissymmetry, which modifies inductances and coupling, especially with the power circuit. This paper describes the analysis of an existing power module. An optimization process based on a modification of the gate circuit geometry allows balancing current during switching phases. This approach will be validated with experimental measurements and applied on an existing module.     

有限元分析软件ANSYS在多芯片组件热分析中的应用

MCM(多芯片组件)的热分析技术是MCM可靠性设计的关键技术之一。基于有限元法的数值模拟技术是MCM热设计的重要工具。文中主要以ANSYS软件为例,介绍利用其对MCM进行热分析的实例。建立了一种用于某种特殊场合的MCM的三维热模型,得出了MCM内部的温度分布,并定量分析比较了空气自然、强迫对流和液体自然、强迫对流情况下对散热情况的影响。研究结果为MCM的热设计提供了重要的理论依据。     

Reliability evaluation of a silicon-on-silicon MCM-D package

This paper presents the results of reliability testing on a multichip module technology with active silicon substrates. The modules use flip-chip technology to attach silicon chips to the active substrate and this assembly is then packaged into a plastic ball grid array package. Performance was evaluated using two custom designed test chips incorporating thermal, thermomechanical, electrical and reliability test structures. A rigorous environmental test sequence including temperature, cycling, humidity, highly accelerated stress test and power cycling were carried out on the demonstrators. A full destructive physical analysis was then performed, consisting of die/substrate shear, wire bond pull tests and microsectioning.     

Real-time computation of thermal constraints in multichip power electronic devices

In this paper, we present an implementation of a thermal modeling method, based on thermal impedances analysis and applied to a multichip module used as a power converter. Analytical functions of thermal impedances are derived from direct measurements of chips temperature with optical fiber sensors. We describe an original algorithm with a recurrent procedure to compute directly and accurately the convolution integrals with high speed performances. Finally, experimental measurements, in real working conditions, have been performed in order to complete the validation of the real-time estimation of the junction temperatures of the power electronic package.     

Experimental validation of a thermal modelling method dedicated to multichip power modules in operating conditions

In this paper, we present an implementation of a thermal modelling method applied to a multichip module used as a power converter. Analytical functions of thermal impedances, with original formulations for the mutuals are defined. They are derived from 3D thermal simulations and experimental validations with direct chips temperature measurements. Finally, simulations are performed in order to improve the capability of our model to assess, with fast computation, the thermal constraints applied on the multichip module in a real operating condition.     

A Force-Directed-Based Optimization Scheme for Thermal Placement Design of MCMs

Thermal management becomes exceptionally critical to both the reliability and operation performance of electronic packages, particularly for multichip modules (MCMs), as packaging and power densities continue increase while packaging dimension continues decrease. The underlying goal of the study is to pursue the minimum system temperature design of MCMs containing a number of chips of equal and/or unequal power through the optimal chip placement design. To deal with the thermal design problems, an effective indirect optimization approach that integrates a modified force-directed (FD) thermal model, a finite-element (FE) technique and an exterior penalty method (EPM) is proposed. In the modified FD thermal model, a novel representation of the repulsive and attractive forces is proposed, and the sum of these forces in the design system, representing the total system chip junction temperature, constructs the objective of the optimization problems. Together with some geometry constraints, the constrained optimization problems are formed, and furthermore, transformed into unconstrained optimization problems using an EPM. The solution of the optimization problems is sought through a direct, iterative search scheme with two proposed placement strategies. The alternative goal of the study is to address the feature and feasibility of these two proposed placement strategies for the current problems. The applicability of the proposed optimization approach is demonstrated through several design applications, and their results are extensively compared against the published data. It turns out that the current optimization approach can be very effective and robust in providing thermal optimal design of MCMs with a minimal total chip junction temperature through optimal chip placement     

Test structures for MCM-D technology characterization

In this paper we present a set of classic and novel test structures addressed to fully characterize multichip module (MCM) technologies. The structures have been implemented and fabricated in our D-type, flip-chip, ball grid array, silicon substrate technology. In this technology, a silicon chip is used as a substrate on which other commercial chips are flipped and soldered by a screen-printing method. These complex technologies have specific test problems that are solved with this approach. We have specially focused on the measurement of the effects of wafer rerouting on CMOS parameters, the chip-to-chip ball contact resistance, thermal behavior, yield, and reliability of the technology. Experimental results are shown, proving that this methodology is suitable for our technology and can also be applied to other different MCM technologies     

Thermal Resistance Measurement of LED Package with Multichips

Thermal transient measurements of high power GaN-based light-emitting diodes (LEDs) with multichip designs are presented and discussed in the paper. Once transient cooling curve was obtained, the structure function theory was applied to determine the thermal resistance of packages. The total thermal resistance from junction to ambient considering optical power is 19.87 K/W, 10.78 K/W, 6.77 K/W for the one-chip, two-chip and four-chip packages, respectively. The contribution of each component to the total thermal resistance of the package can be determined from the cumulative structure function and differential structure function. The total thermal resistance of multichip packages is found to decrease with the number of chips due to parallel heat dissipation. However, the effect of the number of chips on thermal resistance of package strongly depends on the ratio of partial thermal resistance of chip and that of slug. Therefore, an important thermal design rule for packaging of high power multichip LEDs has been analogized.     

用模拟退火算法实现集成电路热布局优化

介绍了一种综合考虑集成电路电学性能指标以及热效应影响的布局优化方法 .在保证传统设计目标 (如芯片面积、连线长度、延迟等 )不被恶化的基础上 ,通过降低或消除芯片上的热点来优化集成电路芯片的温度分布情况 ,进而优化整个电路性能 .并将改进的模拟退火算法应用于集成电路的热布局优化 ,模拟结果表明该方法与传统布局方法相比在保持了较好的延迟与连线长度等设计目标的同时 ,很好地改善了芯片表面的热分配情况     

Response Surface Based Optimization Approach for Thermal Placement Design of Chips in Multiple-Chip Modules

This paper attempts to perform thermal enhancement of planar multiple-chip modules (MCMs) containing a number of chips of equal and/or unequal power through optimal chip placement design. To achieve the goal, an effective design approach is presented for the thermal design optimization problems in the context of models of placement of chips in MCMs. The approach combines the use of the currently proposed response surface (RS) based methodology, which is an optimization algorithm and a finite element modeling technique. The proposed RS-based methodology is used for creating a macro mathematical expression of the design objective of the thermal optimization problem, i.e., the total chip junction temperature of the system, associated with the design parameters, including the chip location and power. The validity of the mathematical expressions constructed is verified through two approaches. Furthermore, to make the constructed mathematical expression more compact while maintaining the associated solution accuracy, the backward variable elimination technique is employed. The effectiveness of the proposed design optimization methodology is demonstrated through several design case studies involving planar plastic ball grid array type MCMs. It is found that the proposed RS-based methodology could accurately define the macro mathematical model of the total system chip junction temperature in terms of the chip location and power. In addition, results show that the current optimal chip placement design can provide a minimal system temperature.     

Evolution of engineering change and repair technology in highperformance multichip modules at IBM

In multichip modules (MCMs), engineering changes (EC) are required for both repair of defective chip to chip connections within the module, as well as modification of electrical connections for module performance optimization. With the recent use of complementary metal-oxide-semiconductor (CMOS) chips in IBM's latest generation of mainframe machines, EC design has been modified to accommodate chips with a much higher number of signal I/Os. Using the previous design methodology of connecting each signal C4 to an EC pad, a large area of the top surface of the module would be required for EC features. This would force increased chip-to-chip wiring length and impact module performance. In addition, larger size MCMs would be required, driving up cost. The new EC approach utilizes top surface thin film wiring in the X and Y directions, which is not pre-connected to any signal C4 pads. The approach used to make desired EC connections is described. New processes were developed to make micro-connections to customize an EC connection, CMOS based MCMs have more than 5× the signal I/Os per chip compared to bipolar devices. As a result of the evolution in EC technology, CMOS chip based MCMs have been successfully designed, built, tested and debugged quickly. They are being used in IBM's latest generation mainframe machines