Multiple block structure-preserving reduced order modeling of interconnect circuits

In this paper, we propose a generalized multiple-block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends the structure-preserving model order reduction (MOR) method SPRIM [R.W. Freund, SPRIM: structure-preserving reduced-order interconnect macromodeling, in: Proceedings of International Conference on Computer Aided Design (ICCAD), 2004, pp. 80-87] into more general block forms. We first show how an SPRIM-like structure-preserving MOR method can be extended to deal with admittance RLC circuit matrices and show that the 2q moments are still matched and symmetry is preserved. Then we present the new BSPRIM method to deal with more circuit partitions for linear dynamic circuits formulated in impedance and admittance forms. The reduced models by BSPRIM will still match the 2q moments and preserve the circuit structure properties like symmetry as SPRIM does. We also show that BSPRIM can build the compact models with similar size and accuracy of that produced by traditional projection based methods but using less computation costs. Experimental results show that BSPRIM outperforms SPRIM in terms of accuracy with more partitions and outperforms PRIMA with less CPU times for generating the same accurate models.     

Fast simulation of multistage power electronic systems with widelyseparated operating frequencies

This paper presents a fast and efficient way of simulating multistage power electronic circuits with different stages operating at widely separated frequencies, using the transmission-line modeling (TLM) technique. A multistage circuit can be modeled as several smaller subcircuits, which can then be simulated individually with different time steps according to their circuit time constants. Energy exchange between linked subcircuits are made possible via the use of a new TLM stub link conversion technique and improved TLM link algorithms. The proposed technique has been tested successfully in a simulation of a switched-mode power supply. Simulation results confirm that the new approach can greatly reduce the computing time of the simulation when compared with conventional TLM simulation methods. A reduction of about two-thirds of the computing time has been achieved in the simulation of a three-stage switched-mode power supply     

Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

We investigate on-chip RLC interconnect reduced order modeling problem. A provably realizable and stable model order reduction approach is proposed. To guarantee stability of reduced order circuits, we first employ a realizable reduction for load approximation to preserve the first three driving-point admittance coefficients. Then, we use Hurwitz polynomials to approximate the denominators of original rational transfer functions. We prove that stability can be guaranteed during a hierarchical analysis while circuit response moments can still be matched implicitly. We also give some experimental results to show the accuracy and efficiency of the proposed approach.     

Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow

Model-order reduction (MOR) is a typical approach to speed up the post-layout verification simulation step in circuit design. This paper studies the benefits of using circuit partitioning in a complete MOR flow. First, an efficient reduction algorithm package comprising of partitioning, reduction, and realization parts is presented. The reduction flow is then discussed using theoretical analysis and simulations from an array of 65-nm technology node interconnect circuits. It is shown that the reduction efficiency and computational costs quickly worsen with increased circuit size when using a direct projection-based MOR approach. In contrast, by using partitioning, the MOR can retain the scalability of the reduction problem, being computationally lighter and more efficient even with larger circuits. In addition, using partitioning may improve the robustness of the MOR flow in cases with circuits with many ports or sensitive verification simulations.     

An efficient terminal and model order reduction algorithm

The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the recently proposed terminal reduction method, SVDMOR [P. Feldmann, F. Liu, Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals, in: Proceedings of the International Conference on Computer Aided Design (ICCAD), 2004, pp. 88-92]. But different from SVDMOR, the new method considers higher order moment information for terminal responses during the terminal reduction and separately applies singular value decomposition (SVD) on both input and output terminals for low-rank approximations. This is in contrast to the SVDMOR method where input and output terminal responses are approximated by SVD at the same time, which can lead to large errors when the numbers of inputs and outputs are quite different. We analyze the passivity requirements for SVD-based terminal and model order reduction and show that the combined passive terminal and MOR using SVD method will not lead an effective terminal reduction in general. Our experimental results show that the proposed ESVDMOR method outperforms the SVDMOR method in terms of accuracy for the same reduced model sizes when the numbers of input and output terminals are quite different.     

互连封装结构电特性分析中的改进PEEC三维建模

本文提出了一种改进的PEEC模型,为便于在大规模互连封装结构分析中利用规模缩减技术,它以描述系统的状态方程代替了具体的等效电路.为此它以矢量磁位的积分表达式和洛仑兹规范代替了矢量磁位和标量电位的积分表达式,对积分方程进行展开.这样做可以避免复杂介质结构中的电容矩阵提取,大大节省了计算时间.这一模型可方便地嵌入更大的系统进行分层次的综合分析和利用PVL等规模缩减技术.数值计算的结果与其他文献吻合较好,表明该方法有较高的可靠性.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

Microwave channelized active filters-a new modular approach toachieving compactness and high selectivity

The new class of microwave active filters being presented offers a convenient way to realize miniature filter circuits with sharp passband-to-stopband transitions. The approach, which lends itself to a broad range of narrowband and wideband filtering applications, involves parallel connections of frequency-selective, unilateral network branches that contain both passive and active subcircuits. Highly selective filtering action derives from controlled interferences among branch signal components. Attributes of the new technique include unconditional circuit stability, tolerance for large passive-circuit-element losses, practicability of narrowband lumped-element configurations, graceful performance degradation with active element parameter changes, and the advantage of module-based procedures for design and implementation. The broad applicability of the new approach is illustrated with three experimental demonstration circuits that employ off-the-shelf MMIC amplifier chips. The circuits comprise a 10-GHz notch filter of one quarter percent bandwidth, a 10-GHz bandpass filter of two percent bandwidth, and a 7.5-GHz lowpass filter     

有耗互连线频变电感提取及等效电路模型

采用二维电感模型，计算了带接地导体的有耗互连线的频变阻抗。阻抗函数用分式多项式近似，并表达为串接的并联电阻、电感的福斯特电路形式。考虑互连线分布电容参数，并根据多个频点阻抗值，用有限数量极点，综合得到互连线单位长度的等效电路模型。采用该模型进行互连线时域响应分析，其结果与改进特征法结果吻合较好，且便于与其他电路模型结合，进行大规模电路的时域分析。     

Numerical Determination of Possible Multiple DC Solutions of Nonlinear Circuits

This paper proposes an approach to find possible multiple solutions of nonlinear resistive circuits. The approach does not guarantee to find all the solutions; its main features are efficiency, the ability to deal with circuits composed of elements described by the most common models employed in microelectronics, such as DIODEs, bipolar junction transistors, MOSFETs and the capability to simulate medium size circuits composed of, but not limited to, some thousand transistors. The proposed approach is based on the partitioning of the original circuit in subcircuits and on the construction of an oriented dependency graph that defines a suitable ordering in the solution of the subcircuits. The oriented dependency graph can have oriented loops and loops can be "sources" of multiple operating points. These loops can be opened by removing a minimal number of circuit nodes. In general these circuit nodes constitute a very small subset with respect to the nodes of the original circuit and as shown in the paper represent a peculiar aspect to search for multiple solutions of a nonlinear circuit.     

256-channel bidirectional optical interconnect using VCSELs andphotodiodes on CMOS

Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems. Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits. The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 0.35-μm complementary metal-oxide-semiconductor (CMOS) chip. The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array. This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

三维互连电感电阻的快速提取

VLSI电路的特征尺寸已降至深亚微米量级,频率已达2GHz.为保证高性能电路设计的正确性,需快速而精确地计算互连寄生电感电阻.本文提出了一种适合三维层次互连结构的描述格式,提出一种考虑趋肤效应的电流细丝自动划分方法,实现了改进的非均匀立方体划分多极加速计算.数值结果表明,在可比精度下,它比当前十分先进的多极加速提取软件FastHenry^[1]快数倍以至数十倍.     

Design Error Diagnosis with Re-Synthesis in Combinational Circuits

A new approach is proposed for removing design errors from digital circuits, which does not use any error model. Based on a diagnostic pre-analysis of the circuit, a subcircuit suspected to be erroneous is extracted. Opposite to other known works, re-synthesis of the subcircuit need not be applied to the whole function of the erroneous internal signal in terms of primary inputs, it may stop at arbitrary nodes inside the circuit. As the subcircuits to be redesigned are kept as small as possible, the speed of the whole procedure of diagnosis and re-synthesis can be significantly increased. A formal algorithm is proposed for the whole procedure. Experimental data show the efficiency of the diagnostic pre-analysis.     

Stable Parallelizable Model Order Reduction for Circuits With Frequency-Dependent Elements

With clock frequencies in the multigigahertz range, wide wires in the power and clock distribution networks suffer from prominent frequency-dependent effects. To overcome the simulation problem of such circuits, a guaranteed stable and parallelizable model order reduction technique is proposed that can handle frequency-dependent elements by construction. The basic idea is to match the output at multiple frequencies with a reduced order function. Once the reduced function is known, it becomes straightforward to calculate the time-domain response. Since this technique works in the frequency domain, it does not require replacement of frequency-dependent elements with equivalent constant RLC subcircuits, significantly reducing the size of equivalent circuits of wide power and clock distribution networks. With parallel computation, the proposed technique obtains time-domain responses in comparable time to calculate the first moment in AWE. Simulations have shown that as few as six frequency points are needed for coupled RC circuits and up to 50 frequency points are needed for complex RLC circuits. To test its ability of handling frequency-dependent elements, a sample circuit with frequency-dependent elements is used that is about 30% of the size of the equivalent circuit with constant RLC elements used in SPICE. In all cases, the proposed technique gives accurate and stable time-domain responses.      

平行光纤互联技术：高性能和低能耗的结合

This paper analyzes the physical potential,computing performance benefit and power consumption of optical interconnects. Compared with electrical interconnections, optical ones show undoubted advantages based on physical factor analysis. At the same time, since the recent developments drive us to think about whether these optical interconnect technologies with higher bandwidth but higher cost are worthy to be deployed, the computing performance comparison is performed. To meet the increasing demand of large-scale parallel or multi-processor computing tasks, an analytic method to evaluate parallel computing performance of interconnect systems is proposed in this paper. Both bandwidth-limit model and full-bandwidth model are under our investigation. Speedup and efficiency are selected to represent the parallel performance of an interconnect system. Deploying the proposed models, we depict the performance gap between the optical and electrically interconnected systems. Another investigation on power consumption of commercial products showed that if the parallel interconnections are deployed, the unit power consumption will be reduced. Therefore, from the analysis of computing influence and power dissipation, we found that parallel optical interconnect is valuable combination of high performance and low energy consumption. Considering the possible data center under construction, huge power could be saved if parallel optical interconnects technologies are used.     

Verification and revision of the power-down mode for hierarchical analog circuits

Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification of the power-down mode of hierarchical analog circuits. In contrast to flat verification approaches, intermediate results are reused during computation. The obtained verification results can be used to revise and correct detected errors. Experimental results for a high input impedance differential amplifier are given.