Warpage simulation and experimental verification for 320 mm × 320 mm panel level fan-out packaging based on die-first process

Warpage for 320 mm × 320 mm panel level fan-out packaging based on die-first process was investigated by both simulation and experimental approaches. In the present paper, a simple and efficient FEA (Finite Element Analysis) method based on shell element was introduced. Finite element models were built by using the software of Ansys products to predict and analysis the warpage for feasibility of large panel fan-out packaging technology in aspect of material, package geometries, package size, process conditions and metal density. In order to verify the accuracy and the precision of the simulation method, test vehicle with dies was fabricated by using low cost ‘die first (face down)’ fan-out technology. Warpage of the test vehicle was measured by using Shadow Moiré method. The simulated warpage result and the experimental one exhibit good consistency.     

Reliability comparison of 28 V–50 V GaN-on-SiC S-band and X-band technologies

This paper discusses the reliability performance of Wolfspeed GaN/AlGaN high electron mobility transistor (HEMT) MMIC released process technologies, fabricated on 100 mm high purity semi-insulating (HPSI) 4H-SiC substrates. The intrinsic reliability performances of the 28 V and 40 V technologies, with 400 nm and 250 nm gate length, have been characterized with DC accelerated life test (DC-ALT), for which ohmic contact inter-diffusion is the wear-out mechanism, and is accelerated by temperature and current. The intrinsic reliability performance of the 50 V technologies, with 400 nm gate length, have been characterized with RF-ALT, for which source-connected second field plate void coalescence is the wear-out mechanism which is accelerated by temperature. In spite of the differences in the accelerated test methodologies and wear-out mechanisms, all of the Wolfspeed GaN-on-SiC technologies demonstrate high and similar predicted lifetimes at their respective maximum recommended operating conditions. The reliability performance is supported with successful technology qualifications with zero failures, and volume manufacturing with a demonstrated low field failure rate.     

A novel 0.84 ppm/°C CMOS curvature-compensated bandgap with 1.2 V supply voltage

This paper proposes a novel CMOS curvature-compensated bandgap reference (BGR) by using a new full compensation technique. The theory behind the proposed full compensation technique is analyzed. The proposed BGR is designed and implemented using 0.15 μm standard CMOS process. Simulation results show that the proposed BGR achieves a temperature coefficient (TC) of 0.84 ppm/°C over the temperature range from −40 °C to 120 °C with a 1.2 V supply voltage. The current consumption of proposed BGR is 51 μA at 27 °C. The line regulation of proposed BGR is 0.023%/V over the supply voltage range from 1.2 V to 1.8 V at 27 °C. In addition, the PSRRs of proposed BGR are −91 dB, −81 dB, −61 dB and −29 dB at DC or 10 Hz, 1 kHz, 10 kHz, and 100 kHz, respectively.     

Improving ESD protection of 5 V NMOSFET large array device in 0.4 μm BCD process

In the output stage of power ICs, large array devices (LAD) of MOSFETs are usually used to drive a considerable amount of current. Electrostatic discharge (ESD) self-protection capability of LAD is also required. ESD layout rules are usually adopted in low voltage CMOS transistors to improve the ESD performance but with a large layout area. In this paper, a modified RC gate-driven circuit with gate signal control circuit is developed to keep the minimum device layout rule while achieving ESD self-protection. Thus, it results in a very small layout area increment while keeps the LAD operates safely in normal operation and gains good ESD protection level.     

Design and fabrication of compact 2 × 2 dual linear polarized wideband and high gain array for Ku-band satellite communication application

In this paper, the design of a planar array antenna for two-way satellite communication is presented. The antenna unit consists of four elements and two waveguide feeding networks used to connect the elements. The radiating elements are small horn apertures. Each element of the array includes two separate ports to radiate vertical and horizontal polarization, respectively. The feeding networks consist of power dividers and bends to connect the vertical and horizontal polarization ports of horns, separately. Radiating elements and feeding networks are designed to cover receive band (10.5–12.75 GHz) and transmit band (13.75–14.5 GHz) within Ku-band. The maximum gain for this type of antenna is 21 dBi.     

−31 dBm sensitivity high efficiency rectifier for energy scavenging

RF energy scavenging is capable in converting RF signals into electricity and has become a promising solution to power energy-constrained wireless networks. However, it has low power conversion efficiency especially when the harvested RF power is small. For this reason, we propose an enhanced differential-drive rectifier to improve the efficiency and the sensitivity of rectifier for energy scavenging applications. The proposed rectifier achieves dynamically controlled threshold voltage and reduces leakage current in the transistors through DTMOS transistor in differential-drive topology. The voltage boosting circuit further increases the sensitivity through step up the input signal before the signal enters the rectifier. The decoupling capacitor shunts the noise of the input signal before the signal is injected into the cross-connected gate reducing the voltage drop and maintaining the PCE of the rectifier. The rectifier is designed based on the 0.18 µm Silterra CMOS process technology. Effects of decoupling capacitors, voltage boosting circuit and output load on PCE of the rectifier have been evaluated. Technology scaling and parasitic effects to the rectifier have also been presented. Performance of N-stages proposed rectifier has been compared with the conventional BTMOS rectifier. The proposed method achieves the highest sensitivity of −31 dBm for 1, 3 and 5 stages rectifiers without the need of off-chip load capacitor.     

A compact 220 GHz heterodyne receiver module with planar Schottky diodes

This letter presents the development of a compact 220 GHz heterodyne receiver module for radars application in which a novel low pass wide stop band intermediate frequency (IF) filter is integrated. The planar Schottky anti-parallel mixing diode based subharmonic mixer (SHM) is used as the receiver’s first stage. The diode is flip-chip mounted on a 50 μm thick quartz substrate. The accurate modeling of the self and mutual inductance of the diode’s air-bridges are discussed. The measured conversion loss (CL) of the SHM has a minimum value of 6.2 dB at 210.5 GHz, and is lower than 8.4 dB in the frequency range 209.4–219.6 GHz with a 10 mW input power from a local oscillator (LO). The LO chain consists of a 110 GHz passive tripler, two Ka-band amplifiers and a Ka-band active tripler. The tested minimum double side band (DSB) noise temperature of the integrated 220 GHz heterodyne receiver is 725 K at 205.2 GHz and lower than 1550 K in the frequency range 199–226 GHz.     

Failure analysis on 14 nm FinFET devices with ESD CDM failure

Electrostatic Discharge (ESD) is an important area for the semiconductor industry because ESD has an impact on production yield and product quality. ESD problems are increasing and have become challenging in the semiconductor industry because of the trends toward higher speed and shrinking in technology node. By continually shrinking the transistor with technology scaling, the process, circuit design, and failure analysis (FA) are getting more challenging. This paper is about FA on a 14 nm Fin-Field Effect Transistor (FinFET) device which has ESD failure after Charged Device Model (CDM) test. In most ESD failure FA, most of the time found Electrical Over Stress (EOS), the important is to understand which process layer or design causing the EOS. At the same time, this paper also discusses the difficulties faced, the FA technique used, the bottleneck of the 14 nm FinFET FA by old technology node FA equipment, and the FA findings. Finally, the ESD failure was identified with Scanning Transmission Electron Microscope (STEM)/Energy Dispersive Spectroscopy (EDS) analysis. The FA findings of the failure are related to the front end of line (FEOL), the metal gate of FinFET was fused with active, and the material in the metal gate was out-diffused.     

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree

The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.     

Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS

The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose differential output current drives a fully differential, high-resistance, transimpedance stage, with an embedded common-mode feedback loop to increase the CMRR. This stage is followed by a differential-to-single-ended output amplifier. Low-power operation has been achieved by exploiting sub-threshold operation of MOS transistors and adopting a supply voltage of 1 V. Simulation results in a commercial 65 nm CMOS technology show a 1 Hz to 5 kHz bandwidth, a CMRR higher than 120 dB, an input referred noise of 8.1 μVrms and a power consumption of 1.12 μW.     

A precision low-power analog front end in 180 nm CMOS for wireless implantable capacitive pressure sensors

This paper presents a new capacitance to voltage analog-front end (AFE) designed in 180 nm CMOS technology for wireless implantable applications. This AFE consists of a Low-dropout regulator (LDO), bandgap reference (BGR), switched-capacitor (SC) sampler, SC op-amp and oscillator. The LDO regulates the wireless power supply coming from an off-chip rectifier and provides a stable and accurate DC voltage. Capacitance is converted to a discrete voltage by a SC sampling circuit and then amplified by a SC op-amp. Both of SC sampling and SC op amp circuits form a correlated double sampling scheme. This AFE is designed to sense a capacitance range from 6 pF to 7 pF (300–1000 mmHg) corresponding to a 0.68 V–1.07 V discrete output voltage with a sampling frequency of 1.63 KHz. This AFE has a sensitivity of 0.39 mV/fF, average power consumption of 201 μW and 3.25% accuracy operating over a 2.1 V–3.3 V rectified wireless supply voltage and −40 °C ~125 °C temperature range.     

A low power high-performance area efficient RF front-end exploiting body effect for 2.4 GHz IEEE 802.15.4 applications

The rising internet-of-things applications in home automation, smart wearables, healthcare monitoring demand small, area efficient, high-performance and low power radio frequency (RF) blocks for effective short-range communication. This growing market demand is addressed in this paper by proposing a fully CMOS radio frequency front-end (RFE) exploiting bulk effect. Apart from the primary function of frequency translation, proper circuit performance concerning the linearity, conversion gain, and noise figure is required for low-cost densely integrated transceivers operating in the 2.4 GHz ISM band. The proposed RFE at 2.4 GHz is designed and implemented in UMC 180 nm CMOS process technology with two modes of operation. In high gain mode (Mode-I), the post-layout simulation with SpectreRF shows a peak gain of 30.06 dB, IIP2 at 64.52 dBm, IIP3 at −2.74 dBm and a DSB-NF of 7.68 dB while consuming only 9.24 mW from the 1.8 V supply. In the high linear mode (Mode-II), the RFE achieves a higher IIP3 of 10.78 dBm, IIP2 of 91.56 dBm, the conversion gain of 23.5 dB, DSB-NF of 9.46 dB while consuming a low power of 3.6 mW. The fully CMOS circuit occupies a core area of only 0.0021 mm². The proposed front-end exhibits a spurious free dynamic range (SFDR) of 81.18 dB ensuring the high dynamic operation of the wireless system.     

A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

In this work, a 9T subthreshold SRAM cell is proposed with the reduced leakage power and improved stability against the PVT variations. The proposed cell employs the read decoupling to improve the read stability, and the partial feedback cutting approach to control the leakage power with improved read/write ability. The incorporated stacking effect further improves the leakage power. The simulated leakage power for the proposed cell is 0.61×, 0.49×, 0.80× and 0.55×, while the read static noise margin (RSNM) is 2.5×, 1×, 1.05× and 0.96×, write static noise margin (WSNM) 0 is 1.5×, 1.8×, 1.68× and 1.9× and WSNM 1 is 0.95×, 1.2×, 1.05×, and 1.2× at 0.4 V when compared with the conventional 6T and state of arts (single ended 6T, PPN based 10T and data aware write assist (DAWA) 12T SRAM architectures) respectively. The minimum supply voltage at which this cell can successfully operate is 220 mV. A 4 Kb memory array has also been simulated using proposed cell and it consumes 0.63×, 0.67× and 0.63× less energy than 6T during read, write 1 and write 0 operations respectively for supply voltage of 0.3 V.     

The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications

In this paper three delay cell structures used in four-stage ring oscillator are evaluated. In the first structure, the control voltage is employed to the gate of PMOS transistors which are inserted in series with the input PMOS transistors. In this case the minimum power dissipation is gained. Since the control voltage is injected to the PMOS transistors parallel with input transistors, the better tuning range in higher frequency and lower phase noise is achieved. In order to make a tradeoff between the tuning range, phase noise and power dissipation, the PMOS transistors activated with the control voltage are applied to the oscillator in both the series and parallel paths. In improved structure, the oscillator works in 2.65–13.93 GHz under 1 V supply voltage in 65 nm CMOS technology. The phase noise is −94.33 dBc/Hz at 1 MHz offset from 3.7 GHz center frequency, while the power dissipation is 328.6 μW and the chip area is 139.5 µm².