超高频RFID读写器设计

为满足市场需求,提高读写器读写效率,降低成本,提出了一种基于ISO/IEC 18000-6C的射频身份识别(RFID)读写器方案.该读写器适用于超高频段,支持跳频,发送通路来用射频发送芯片,接收回路采用相关解调,用分离元件搭建,成本较低,结构简单,易于实现.采用随机槽时隙陈计数器算法进行防碰撞设计,在多标签环境下能够识别标签,并与其成功通信.相对于采用传统随机碰撞算法的读写器,此读写器能够在多标签环境下顺利读取标签,防碰撞性能具有一定提高.     

基于0.5μm CMOS工艺的13.56MHz RFID读写器解调电路

射频识别系统主要包括读写器和电子标签两部分.设计了一种新颖的13.56MHz读写器芯片核心部分信号链路,包括混频、滤波、放大模块、积分模块、采样保持模块以及位解码模块.该结构能够提高接收电路的灵敏度和抗干扰能力.设计遵循ISO/IEC 14443协议Type A,采用一种5V单电源0.5μm CMOS工艺,给出了Cadence环境下的仿真结果.     

物联网中UHF频段RFID读写器设计

基于物联网中数据采集的需要,设计了一个UHF频段便携式RFID读写器。介绍了读写器的工作原理,重点阐述了射频前端电路的设计。用专用芯片AS3992及其外围电路完戍射频信号的收发,用STM32系列单片机完成基带信号处理和控制。还简单介绍了系统的软件工作流程以及低功耗设计的细节。测试结果表明：该读写器支持ISO／IEC18000—6B／6C协议,具备小型化、远距离、低功耗、易扩展等特点,能满足智能物联网的实际需要。     

符合ISO/IEC 18000-6C标准的UHF RFID读写器设计

在超高频段,ISO/IEC 18000-6标准中6B多用于交通领域,而6C主要用于物流、生产管理和供应链管理领域.分析了ISO/IEC 18000-6 C标准,基于此标准设计了一种超高频射频识别读写器.详细阐述了读写器的软硬件设计,其中硬件设计主要包括射频发送电路、射频接收电路和数字基带处理电路.读写器软件设计中叙述了整体设计结构、基于概率、槽计数器的防冲突算法、发送接收链路的数据编解码设计、16 bit CRC校验以及读写器对标签操作命令流程.     

基于非接触式IC卡的考勤系统设计

本文研究了射频识别系统的工作原理,并对射频识别系统的构成、数据传输原理、基本工作流程、系统的分类、编码和调制以及数据的完整性给出了较为详细的理论研究。并对非接触式IC卡与读写器的通讯过程和电磁工作原理进行了简单的描述。描述了非接触式IC卡的国际标准ISO/IEC14443协议,通过协议能更好地理解卡片与读写器间的传输过程,有利于下文读卡器的硬件设计和MCU的主程序实现。最后,本文在射频理论的基础上进行了读写器的软硬件设计。     

远距离RFID读写天线的研究

自动识剐技术是将信息数据自动识读、自动输入计算机的一种重要方法.接触式识剐易受恶劣环境影响且易受机械磨损,而射频识别(REID)技术以非接触性解决卡中无源和免接触等难题.通过研究射频天线各种性能参数,提出一种远距离RFID读写天线的设计优化方法,使频率为13.56 MHz,遵循ISO15693协议的RFID读写器有效读写距离拓展到30 cm左右,实现RFID读写器的远距离读写功能.     

手持式超高频RFID读写器天线设计技术综述

天线作为手持式超高频射频识别技术(Radio frequency identification technology,RFID)读写器中的关键部件,其性能直接影响到RFID系统的读写距离和读写器体积大小.论文分析研究各种手持式超高频RFID读写器天线的设计技术,重点介绍应用最广的微带天线设计方法、技巧及发展趋势.     

一种13.56MHz无源射频识别模拟前端的设计

提出了一种基于ISO/IEC18000-3协议的高频13.56MHz射频识别(RFID)标签芯片的模拟前端电路结构,采用Chartered 0.35μm EEPROM工艺进行流片验证。该芯片实现了无源RFID标签芯片通信时所需的整流、稳压供电、时钟恢复、信号解调以及副载波调制的全部功能。     

远距离RFID读写天线的研究

自动识别技术是将信息数据自动识读、自动输入计算机的一种重要方法。接触式识别易受恶劣环境影响且易受机械磨损,而射频识别（RFID）技术以非接触性解决了卡中无电源和免接触等难题。通过对射频天线各种性能参数的研究,分析出了远距离RFID读写天线的设计优化方法．使工作频率为13．56MHz．遵循ISO15693协议标准的RFID读写器有效读写距离拓展到30cm左右,实现了RFID读写器的远距离读写功能。     

UHF RFID读写器系统设计

为了分析UHF RFID读写器系统抗干扰性能,提出了基于ISO18000-6 type B 协议下UHF RFID读写器的设计方法,并对其通信过程进行了Simulink仿真,给出了曼彻斯特编解码以及2ASK调制解调的模型。结合实际中经常遇到的高斯白噪声信道分析了系统的信道抗干扰性能,给出了系统的误码率随信噪比变化曲线。仿真表明该UHF RFID读写器系统具有较高的抗干扰性能。     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

GaAs数字电路输入输出接口电路的设计

本文讨论了ＧａＡｓ电路和ＳｉＥＣＬ电路的输入输出接口问题，对ＧａＡｓ电路中ＢＦＬ、ＤＣＦＬ、ＳＤＦＬ等电路形式的典型输入输出接口电路进行了分析研究，用电路模拟程序计算并给出了ＢＦＬ输入输出接口电路的转移特性曲线。     

Switched-current (SI) integrators with reduced effect of transistor mismatches

Switched-current (SI) circuits are widely used for analog sampled-data signal processing, due to their compatibility to the pure digital CMOS process. As their main building blocks are current mirrors, they suffer from the effects of MOS transistor parameters mismatch. In this paper, the Functional Block Diagram (FBD) of already known integrator circuits is modified in such a way that the number of required current mirrors is reduced. Thus, the behavior of the derived integrator topologies, with respect to the effect of MOS transistor parameters mismatch, is improved.A comparison is performed, concerning the performance of the proposed bilinear integrator circuits and those that are already introduced in the literature. For this purpose, a fifth-order Chebyshev lowpass SI filter transfer function was simulated. In the case of the proposed filter configurations, the obtained results show that their performance is improved in terms of the effects of MOS transistor parameters mismatch, DC power dissipation, and total required silicon area.     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

High-efficiency bipolar transconductors composed of hyperbolic function circuits with an intermediate voltage terminal and a triple-tail cell

Relatively high transconductance in bipolar devices contributes to the economy of power dissipation on analog integrated circuits. Recently, a high-speed transistor, such as the HBT attracts attention of researchers and developers in electronic communication industries and is expected to be applied to RF circuits. In this paper, high-efficiency bipolar transconductors are presented. The proposed circuits are composed of a hyperbolic function circuit with an intermediate voltage terminal and a triple-tail cell. The parameter values for linearisation are all integers. The values can be realised precisely. The linearity of the proposed transconductors is superior to the triple-tail cell. The linear input range is 1.5 times as wide as that of the conventional triple-tail cell. Nevertheless, the power dissipation is lower than the triple-tail cell. Further, sensitivity analysis shows that the proposed transconductors have lower sensitivity than the triple-tail cell. These properties are confirmed by SPICE simulation.     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

Current-mode capacitorless integrators and differentiators for implementing emulators of fractional-order elements

Fractional-order capacitor and inductor emulator, implemented using current-mirrors as active elements and MOS transistors as capacitors, is introduced in this paper. Current-mirror integrators are used for performing the required current-mode integration/differentiation operation within the emulator stage. Also, a voltage-to-current converter, implemented using an Operational Transconductance Amplifier, is utilized for realizing the required interface of the input signal. Thus, the proposed emulator is simultaneously capacitorless and resistorless and offers the advantage of electronic tuning of the characteristics as well as of the type of the emulated fractional-order element. In addition, a modified version of the emulator that allows current excitation is proposed. The evaluation of the behavior of the proposed schemes has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.     

Switched-Current Wave Filters with Reduced Number of Current Inversions

Switched-current wave filters offer very simple structures, as their main building blocks are current mirrors. On the other hand, the achieved accuracy is mainly degraded due to the effect of MOS transistor parameters mismatch. In this Letter, new configurations of serial and parallel adaptors that are used in the simulation of inductances and capacitors of the LC ladder prototype are introduced. These have been implemented using an appropriate sharing of the delay that should be presented between the incident and reflected waves at a port of adaptor, and a 3-phase clocking scheme. The number of required current inversions and consequently the effect of mismatching are reduced in the proposed configurations.     

含源T形电路和含源Ⅱ形电路的等效变换

本文讨论了含源T形电路和含源Ⅱ形电路的等效变换,扩展了T形电路和Ⅱ形电路等效变换的内容。根据含独立电源二端口网络的特性方程,推导了含源T形电路和含源Ⅱ形电路等效变换的条件。含源T形电路和含源Ⅱ形电路等效变换的结果不具有唯一性,但可通过附加一些条件使变换结果唯一,本文给出了这些附加条件。并通过实例说明了推导结果的正确性。本文的分析对电路教学具有一定的价值,可供教学参考。     

含独立源T-Π形电路等效变换的几个结论

本文讨论了含独立电源T形电路和Π形电路的等效变换,总结了几个相关的结论并给出了证明。这些结论扩展了T形电路和Π形电路等效变换的内容。通过实例说明了这些结论的正确性。本文的分析对电路课程教学具有一定的价值,可供教学参考。