一种全搜索块匹配运动估计VLSI结构

提出了一种新的两维全搜索运动估计VLSI结构。该结构基于两维脉动阵列,能够完全实现两维数据重用,减少了对外部存储器数据量的访问,具有100%的硬件效率和高吞吐率。该结构也可以很容易地应用于不同块尺寸、不同的搜索范围的全搜索块匹配运动估计,具有通用性。     

一种采用压缩阵列的新型自适应块匹配运动估值器

在视频图像压缩编码中，运动估值计算量巨大、其硬件实现极富挑战性，本文提出一种采用压缩阵列的新型低频滞块匹配运动估值器结构，该结构既能够有效地实现全搜索，又能够实现如三步搜索等快速分层搜索算法，与传统的累加树型结构相比，其运行效率显著提高，而芯片面积进一步减少，在此基础上，本文还提出一种自适应夫匹配和硬件实现方法，使块匹配运算量再降低约１／２－１／４，并以很小的硬件开销进一步降低了延滞。     

运动估计的分层搜索算法及FPGA实现

针对H．263，MPEG4 SP等低比特率的视频编码特点，在全搜索块匹配算法的基础上提出了一种适合在硬件上实现的运动估计新算法，以及实现这一算法的硬件结构。这种结构充分利用硬件资源，采用了并行结构及数据复用技术，从而大大节省计算时间。对于CIF格式的图像，运动矢量搜索范围为-16～ 15．5，帧速率可达25帧／s。     

一种用于块运动估计的匹配准则函数块特征匹配函数

本文提出了一种新的块运动估计匹配准则函数块特征匹配(BFM)函数,可以用于视频压缩的一些国际标准,如H.261,H.263,MPEG1,MPEG2,HDTV的编解码器中。在这些视频压缩国际标准中视频系统编码器的复杂性最主要取决于运动估计算法。实时的块匹配运动估计的VLSI实现需要考虑以下几个方面:在给定搜索域内运动搜索的复杂度;每次块匹配运算的匹配计算复杂度;每次块匹配运算需要从帧存读取到运动估计处理器的数据量大小;实时硬件实现的适用性.仿真表明BFM算法非常简单有效,可以大大降低相应的块匹配计算复杂度、匹配运算时数据传输时间.BFM函数便于并行实现,从而可以有效地缩短视频编码器的编码时间。本文还详细地给出了BFM函数与其它常用匹配准则函数的比较结果.     

Research of Block Matching Image Stabilization Algorithm Based on DM642

应用全搜索的块匹配法,对平移抖动的的视频序列在DM642平台上进行了稳像处理.该块匹配法在当前帧上均匀的选取6个小块,然后在±30像素范围内在参考帧上搜索匹配块,剔除不准确的运动位移值后得出抖动帧的位移值.实验结果表明,该块匹配法对抖动的视频序列有一定的稳像效果.     

基于DM642的块匹配稳像算法的研究

应用全搜索的块匹配法,对平移抖动的的视频序列在DM642平台上进行了稳像处理。该块匹配法在当前帧上均匀的选取6个小块,然后在±30像素范围内在参考帧上搜索匹配块,剔除不准确的运动位移值后得出抖动帧的位移值。实验结果表明,该块匹配法对抖动的视频序列有一定的稳像效果。     

用于H.264的高性能整像素运动估计VLSI的设计

给出了一种用于H.264变块尺寸全搜索块匹配算法的运动估计电路的改进结构,并完成了VLSI设计。通过脉动阵列和全流水线的设计,达到最高的数据重用率、最小的I/O引脚数和100%的硬件计算效率。采用HJTC 0.18μm 1P6M CMOS工艺,完成了运动估计芯片的VLSI实现,芯片面积为4 mm×4 mm,最高工作频率125 MHz。仿真表明,本设计能实时处理SHDTV(1920×1080,60 f/s)视频序列,满足H.264的应用需求。     

完全搜索块匹配运动补偿算法光电混合系统

基于声光相关器提出了种能实时实现视频图象压缩中完全搜索块匹配运动补偿算法的光电混合系统，与全数字电路相比，该系统具有足够的带宽，能并行处理大量数据，并且电路较简单，可降低功耗、成本及结构复杂性，还讨论了该系统的适用范围。     

基于节点搜索的可变形块运动补偿

本文讨论可变形块匹配(DBMA)的运动补偿和预测方法,提出基于节点搜索的可变形块匹配算法(NS-DBMA),并在此基础上提出分数像素精度预测和双模式混合预测方法.实验结果表明,NS-DBMA比全搜索方块匹配法(EBMA)平均改善约2dB;其运算量仅为基于梯度的可变形块匹配算法(GB-DBMA)的一半,但能得到更好的主客观预测质量,且更易于VLSI硬件实现.     

一种低功率分层运动估值器的VLSI结构设计

本文提出一种新的低功率分层运动估值器的VLSI结构,它支持低比特视频编码器的高级预测模式,如H.263和MPEG-4。为减少芯片尺寸及功率消耗,在所有搜索层中使用同一个基本的搜索单元 (BSU)。另外,通过对数据流的有效控制,使其在高级预测模式下,在获得宏块运动矢量的同时,也获得每个宏块中的4个88子块的运动矢量。实验结果表明,这种结构采用较少的门电路,有效降低了功率消耗,并且实现了与全搜索块匹配算法(FSBMA)相似的编码效果,可广泛应用于无线视频通信所需的低功率视频编码器中。     

一种基于流处理框架的可重构分簇式分组密码处理结构模型

可重构密码处理结构是一种面向信息安全处理的新型体系结构,但具有吞吐量和利用率不足的问题。该文提出一种基于流处理框架的阵列结构可重构分组密码处理模型(Stream based Reconfigurable Clustered block Cipher Processing Array, S-RCCPA)。针对分组密码算法特点,采用粗粒度可重构功能单元、基于Crossbar的分级互连网络、分布式密钥池存储结构以及静态与动态相结合的重构方式,支持密码处理路径的动态重组,以不同并行度的虚拟流水线执行密码任务。对典型分组密码算法的适配结果表明,在 CMOS工艺下,依据所适配算法结构的不同,规模为41的S-RCCPA模型的典型分组密码处理性能可达其它架构的5.28~47.84倍。     

FPGA Implementation(s) of a Scalable Encryption Algorithm

SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards, or processors. In this letter, we investigate its performances in field-programmable gate array (FPGA) devices. For this purpose, a loop architecture of the block cipher is presented. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. The letter also carefully describes the implementation details allowing us to keep small area requirements. Finally, a comparative performance discussion of SEA with the advanced encryption standard Rijndael and (a cipher purposed for efficient FPGA implementations) is proposed. It illustrates the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency.     

一种新的使用两种比特分辨率图象的块匹配运动估计算法及其低功耗VLSI结构

本文给出了一种新的块匹配运动估计算法,它根据视频图像内容的复杂程度自适应地选择常规的或者低比特分辨率的图像来进行块匹配,并且采用了一种混合使用两种比特分辨率图像的新望远镜搜索算法.模拟结果表明,新算法具有较低的计算复杂性,并且能够保证较好的视频质量.基于该算法,我们设计了一种新的脉动阵列结构的搜索引擎.该引擎具有可分割的数据通道,从而在使用低比特分辨率图像进行块匹配时能够通过加强处理的并行性来提高吞吐率.新的运动估计器可工作在较低的时钟频率和电源电压之下,具有低的功耗消耗.     

Edge‐Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture

This paper presents a new edge‐protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge‐protection maps. Based on these maps, a two‐step adaptive filter which includes offset filtering and edge‐preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory‐reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.     

Conservative Approximation–Based Full‐Search Block Matching Algorithm Architecture for QCIF Digital Video Employing Systolic Array Architecture

This paper presents a power‐efficient hardware realization for a motion estimation technique that is based on the full‐search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register–based 2‐D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.     

Low area field-programmable gate array implementation of PRESENT image encryption with key rotation and substitution

Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultra-lightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.     

Parallel processing architectures for rank order and stack filters

Many architectures have been proposed for rank order and stack filtering. To achieve additional speedup in these structures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential for additional speedup when the original architecture has reached the throughput limits caused by the underlying technology. A trivial block structure simply repeats a single input, single output structure to generate a multiple input, multiple output structure. Therefore the architecture can achieve speedups equal to the number of multiple outputs or the block size. However, unlike linear filters, the rank order and stack filter outputs are calculated using comparisons. It is possible to share these comparisons within the block structure and thus substantially reduce the size of the block structure. The authors introduce a systematic method for applying block processing to rank order filters and stack filters. This method takes advantage of shared comparisons within the block structure to generate a block filter with shared substructures whose complexity is reduced by up to one-third compared to the original filter structure times the block size. Furthermore, block processing is important for the generation of low power designs. A block structure can trade its increased speedup for a throughput equal to the original single output architecture but with a significantly lower power requirement. The power reduction in the trivial block structures is limited by the power supply voltage. They demonstrate how block structures with shared substructures allow them to continue decreasing the power consumption beyond the limit imposed by the supply voltage     

FPGA Implementation(s) of a Scalable Encryption Algorithm

SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards, or processors. In this letter, we investigate its performances in recent field-programmable gate array (FPGA) devices. For this purpose, a loop architecture of the block cipher is presented. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. The letter also carefully describes the implementation details allowing us to keep small area requirements. Finally, a comparative performance discussion of SEA with the Advanced Encryption Standard Rijndael and ${tt ICEBERG}$ (a cipher purposed for efficient FPGA implementations) is proposed. It illustrates the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency.      

Design of a high performance memory using a novel architecture of double bit CAM and SRAM

A high-speed low-power novel architecture of Dual Bit Content Addressable Memory (DB-CAM) is reported in this article. A low leakage, low power and high-speed memory has been developed using the novel architecture of DB-CAM that can store 2 bits in a single CAM block and Static Random Access Memory (SRAM). Data search operation is done by using CAM cells and SRAMs are used as data storage cells. The output of SRAM cells depend on the search result of CAM cells. To make the search operation more precise a priority detector circuit has been proposed. The new architecture of DB-CAM block reduces the power consumption, transistor count and the area on chip enormously. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre (CADENCE) using standard 90?nm CMOS technology.