氮化硅湿法蚀刻中热磷酸的蚀刻率

在半导体湿法蚀刻中,热磷酸广泛地用于对氮化硅的去除工艺,实践中发现高温下磷酸对氮化硅蚀刻率很难控制.从热磷酸在氮化硅湿法蚀刻中的蚀刻原理出发,分析了影响蚀刻率的各个因素,并通过实验分析了各个因素对蚀刻率的具体影响.根据目前广泛应用于生产中的技术,介绍了如何对相关因素进行控制调节,为得到稳定的热磷酸蚀刻率提供了方向.     

MEMS/Sensor工艺中无定形碳应用及干法蚀刻研究

提出一套新的无定型碳牺牲层蚀刻工艺,新工艺应用于MEMS和Sensor牺牲材料工艺中,能够很好地解决无定形碳蚀刻工艺中有机副产物问题。在无定形碳蚀刻工艺中添加低浓度的CF4蚀刻气体(1%~5%),有助于去除在蚀刻过程中侧壁形成的有机副产物。在无定形碳蚀刻工艺前添加一步光刻胶硬化步骤,和在无定形碳蚀刻工艺后添加一步有机副产物各项异性蚀刻步骤,有助于去除表面产生的有机副产物。并针对新工艺去除无定形碳蚀刻过程中形成的有机副产物反应机制进行了详尽阐述与讨论。     

蚀刻在PCB生产中应用和工艺控制

本文以实验的方法确定蚀刻速度与各参数的关系,控制蚀刻质量的精确度,减少蚀刻过程中侧蚀现象,并详细介绍喷琳蚀刻液在复杂三维曲面上制作精细图形的工艺过程,阐述了在工艺操作过程中应注意的诸多因素,制作精细线宽/间距精度达到2mil/2mil。     

碱性蚀刻的不良分析和改善

蚀刻工艺是印制线路板制作过程中一个非常重要的步骤,怎样提高蚀刻均匀性,降低蚀刻报废,非常的重要。设计方面:不同厚度的底铜做相应的补偿;设备方面:要从喷咀类型、喷咀方向、喷咀到板距离、蚀刻抽风量、蚀刻液的喷淋压力、防卡板上控制;药水和工艺方面:要从配制子液、蚀刻母液的氯铜比、蚀刻液温度、蚀刻液PH值等进行控制;检验方面:要从首末件的确认上控制批量蚀刻不良的流出。     

微带蚀刻工艺影响因素探讨

本文阐述了在微带精密蚀刻过程中影响蚀刻速率变化的诸多因素,探讨了酸性氯化铜蚀刻液工艺控制应该注意的问题和解决办法。     

二氧化硅干法蚀刻参数的优化研究

阐述了二氧化硅干法蚀刻的原理和主要的蚀刻参数.应用正交实验,进行了蚀刻速率、均匀性、选择比等主要蚀刻参数的优化,得出主要工艺参数的设置方法和理想条件漂移时的调整方法以及优化选择比的蚀刻方案.     

电调整微蚀刻

评述了采用电调整微蚀刻试验表明,它适用于各种各样的线宽和间距的精细导线的制造。比起常规喷射蚀刻工艺来,其侧蚀小、蚀刻因子和tanθ高的效果。     

减成法制作双面COF印制电路板工艺研究

双面COF基板可以极大地缩小基板面积,满足产品的轻、薄、短小的要求,因此对于双面COF基板的需求也会逐渐增长.减成法工艺是生产FPC产品的主要工艺,技术与设备都非常成熟.本文对减成法工艺制作双面COF印制板进行了初步研究,讨论了微孔清洗方法的选择,比较了化学镀铜与黑孔化工艺的优劣,对应用液态感光抗蚀剂时的参数如曝光能量、显影速度、蚀刻速度及蚀刻压力等进行了优化,得到最佳工艺流程及工艺参数.     

磁约束反应离子蚀刻装置的磁场优化

应用有限元分析方法建立了多磁极约束磁增强型反应离子蚀刻装置内部的磁场分布模型.通过研究磁极的配置及磁化方向的调整,对蚀刻装置内部磁场的强度及其分布的均匀性进行了优化研究,获得了在兼顾蚀刻速率和蚀刻均匀性的最优工艺要求.     

无故障蚀刻

电路板的蚀刻系统是由化学药品与机器设备组成的。如果蚀刻剂适用于产品而且又能保持一定的浓度,那么这种化学药品就能持续产出线路边缘整齐的电路板。如果蚀刻机械也处于良好状态时,则电路板生产就能很平稳地转送到下道工序。 选择蚀刻剂和浓度应是工艺工程师和化学工程师的责任,尽管机器是由操作工日常操作的,但工艺工程师也应负责选择蚀刻机,因为一台蚀刻机也是整个工厂大     

Bipolar技术中多晶发射极的腐蚀

在现代比较先进的Bipolar技术中,一般采用多晶发射极结构,这种结构可以提高双极管放大倍数和频率响应特性,因此,这种结构得到广泛的应用。由于这种结构中多晶是直接和硅衬底接触的,多晶腐蚀时要注意过腐蚀量、腐蚀均匀性以及腐蚀后硅衬底的形貌问题。本文主要介绍在这种工艺过程中我们进行的相关实验以及控制方法。最后,简单介绍我们工艺开发的第一批结果。     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Experimental optimization of solar cells edge junction passivation

We have developed in this study a simple procedure to determine the optimal etching time to passivate the parasitic edge junction of solar cells. The principle of the technique is based on the control of cells electrical characteristics evolution during the gradual elimination of this edge junction. Using plasma technique, the experiments were conducted on monocrystalline and multicrystalline 4 in silicon solar cells round and square in shape respectively. For monocrystalline silicon, the edge junction etch rates of 55.5 nm/min and 90.0–96.5 nm/min has been found for a batch of 20 cells with chemically phosphorus silica glass (PSG) etched and non-etched respectively. The deduced selectivity S=Si/PSG is about 10. For a batch of 100 multicrystalline silicon solar cells, 34 min were sufficient to remove 0.4 μm parasitic junction depth. For the three batches, the difference between the etch rates is explained by the phosphorus concentration and silicon loading effect. As well as for etching uniformities, they are considered good to acceptable.     

A planarized SiO2interlayer dielectric with bias-CVD

A Bias-CVD^TMprocess has been developed for depositing planarized silicon dioxide films. The process uses, in addition to PECVD deposition, an argon ion etch for planarization. A distinguishing feature of this process is the use of a unique sequence of depositions and etching to control contour and topography, eliminate keyholing, and reduce pinhole density. By varying this Sequence, the film topography can range from conformal to fully planarized. A cold-wall low-pressure CVD system with an eight-wafer batch and 13.56-MHz RF capability was used in this study. Because of the chamber geometry, a dc bias is induced in the wafer support during the RF plasma processing. This bias, typically a few hundred volts, provides the accelerating field for the ion etching of the film. It is the anisotropy of this etch that makes planarization possible. The film has the density and index of refraction of thermally grown oxide. The Si to O ratio is 1 to 1.9 with 8-percent nitrogen and 0.1-percent argon, by RBS. SIMS analysis shows no trace of heavy metals. The effect of process parameters has been characterized. Dynamic RAM's deposited with the sloped film show normal yield and electrical properties; there is no evidence of radiation damage.     

Supervisory run-to-run control of polysilicon gate etch using insitu ellipsometry

Polysilicon gate etch is a critical manufacturing step in the manufacturing of MOS devices because it determines the tolerance limits on MOS circuit performance. The etch used in the current study suffers from machine aging, which causes processing results to drift with time. Performing the etch for the same time with fixed process setpoints (recipe) for all wafers would produce unsatisfactory results. Thus, an in situ ellipsometer was employed with a new run-to-run supervisory controller, termed predictor corrector control (PCC), to eliminate the impact of machine and process drift. A novel modeling technique was used to predict uniformity from the ellipsometry data collected at a single site on the wafer. Predictive models are employed by the PCC supervisory controller to generate optimal settings (recipe) for every wafer which will achieve a target mean etch rate, while maintaining a spatially uniform etch. A 200 wafer experiment was conducted to demonstrate the benefits of process control. Implementation of PCC resulted in a 36% decrease in standard deviation from target for the mean etch rate. In addition, the data indicates that controlling etch rate may improve the control and uniformity of the line width change     

Effects of controlled texturization of the crystalline Si surfaceon the SiO2/Si effective barrier height

A two-stage plasma etch texturination process to control the level of crystalline silicon surface roughness has been investigated. Initially, a Cl₂ plasma etch is used to produce a very rough Si surface. This is followed by an isotropic SF₆ plasma etch, whose etch time is used to reduce and control the level of surface roughness created by the previous step. Oxides grown on texturized Si surfaces with short SF₆ etch times exhibit lower effective SiO₂/Si barrier height and greater electron injection enhancement than those with longer SF₆ etch times     

采用数据流模式提高乱序执行密码芯片的安全性

乱序执行是密码芯片设计中一种低冗余、低功耗的抵抗功耗分析攻击的方法.芯片安全性随着操作执行时刻不确定度的增加而提高.基于数据流模式的乱序执行AES加密集成电路采用动态数据流结构、对并发操作串行地随机服务,通过增加顺序无关操作的数量和成批处理令牌提高不确定度.其中采用了新的令牌暂存-匹配-发射结构完成令牌的同步和对随机执行的控制.实验芯片的所有操作均实现了不确定执行,可以抵抗样本数小于15000的相关功耗分析攻击,芯片功耗低于所知的其它抗功耗分析攻击AES芯片.     

A study in dynamic neural control of semiconductor fabricationprocesses

This paper describes a generic dynamic control system designed for use in semiconductor fabrication process control. The controller is designed for any batch silicon wafer process that is run on equipment having a high number of variables that are under operator control. These controlled variables include both equipment state variables such as power, temperature, etc., and the repair, replacement, or maintenance of equipment parts, which cause parameter drift of the machine over time. The controller consists of three principal components: 1) an automatically updating database, 2) a neural-network prediction model for the prediction of process quality based on both equipment state variables and parts usage, and 3) an optimization algorithm designed to determine the optimal change of controllable inputs that yield a reduced operation cost, in-control solution. The optimizer suggests a set of least cost and least effort alternatives for the equipment engineer or operator. The controller is a PC-driven software solution that resides outside the equipment and does not mandate implementation of recommendations in order to function correctly. The neural model base continues to learn and improve over time. An example of the dynamic process control tool performance is presented retrospectively for a plasma etch system. In this study, the neural networks exhibited overall accuracy to within 20% of the observed values of .986, .938, and .87 for the output quality variables of etch rate, standard deviation, and selectivity, respectively, based on a total sample size of 148 records. The control unit was able to accurately detect the need for parts replacements and wet clean operations in 34 of 40 operations. The controller suggested chamber state variable changes which either improved performance of the output quality variables or adjusted the input variable to a lower cost level without impairment of output quality     

Electron cyclotron resonance plasma etching of HgTe-CdTe superlattices grown by photo-assisted molecular beam epitaxy

In order to form HgTe-CdTe superlattice diode arrays, a well-controlled etch process must be developed to form mesa structures on HgTe-CdTe superlattice layers. Wet etch processes result in nonuniform, isotropic etch profiles, making it difficult to control etch depth and diode size. In addition, surface films such as a Te-rich layer may result after wet etching, degrading diode performance. Recently, a dry etch process for HgTe-CdTe superlattice materials has been developed at Martin Marietta using an electron cyclotron resonance plasma reactor to form mesa diode structures. This process results in uniform, anisotropic etch characteristics, and therefore may be a better choice for etching superlattice materials than standard wet etch processes. In this paper, we will present a comparison of etch processes for HgTe-CdTe superlattice materials using electron microscopy, scanning tunneling microscopy, surface profilometry, and infrared photoluminescence spectroscopy to characterize both wet and dry etch processes.     

Methodology for feedback variable selection for control of semiconductor manufacturing processes - Part 2: Application to reactive ion etching

The PVVM methodology for feedback variable selection introduced in a companion paper (Patterson et al., 2003) is applied to a gate etch process. The primary purpose of this paper is to illustrate the practical aspects of utilizing this methodology. Particular attention is given to the challenging task of process modeling. The model-building procedure and constraint-limited exhaustive search is demonstrated to perform superior to other model-building procedures including principal component regression and partial least squares regression for use in this methodology. A second purpose is to present the results for the etch process. Advanced sensors considered for real-time process control of this process include an RF probe, mass spectroscopy and optical emission spectroscopy. Feedback variables are selected to reduce variation in etch rate, nonuniformity and lateral etch rate. The advantages of treating location on the wafer as a disturbance to the etch rate model so that both etch rate and nonuniformity may be captured in one model are presented and experimentally verified.