TC~2CLA的混合模块延迟公式及优化序列

为提高长加法器的运算速度,扩展操作位数,提出了一种加法器结构--混合模块顶层进位级联超前进位加法器(TC2CLA).该结构将层数Mi>1的CLA模块底层进位级联改为顶层超前进位单元进位级联.在CLA单元电路优化和门电路标准延迟时间tpd的基础上,由进位关键路径推导出混合模块TC2CLA的模块延迟时间公式,阐明了公式中各项的意义.作为特例,导得了相同模块TC2CLA的模块延迟时间公式.并得出和证明了按模块层数递增级联序列是混合模块TC2CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列.这一结论成为优化设计的一个设计规则.还给出了混合模块级联序列数的公式和应用实例.TC2CLA和CLA的延迟时间公式表明,在相同模块序列和不等待(组)生成、传输信号的条件下,最高位进位延迟时间及最高位和的最大延迟时间减小.     

混合模块TC~2CLA无等待时间序列及性质

在不增加顶层进位级联超前进位加法器(TC2CLA)模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块TC2CLA的延迟时间公式的基础上提出了混合模块顶层级联超前进位加法器无等待时间序列.给出了混合模块TC2CLA无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及一系列重要性质.     

混合模块无等待时间序列超前进位加法器设计

在不增加超前进位加法器模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块超前进位加法器(CLA)延迟时间公式的基础上提出了混合模块无等待时间序列超前进位加法器.给出了混合模块CLA的无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及重要性质.并在功耗、面积(资源)占用约束下,优化设计了操作位数复盖范围为10～854位的94个混合模块无等待时间序列超前进位加法器.实现了保持CLA模块速度条件下,最大限度地扩展操作位数的目的.     

混合模块TC~2CLA优化设计的结构参数约束

在顶层进位级联超前进位加法器（TC2 CLA）基本单元及组合方案优化设计的基础上,将微电子技术工艺水平制约下的门电路最大扇入数Nfanin（max）和扇出数Nfanout（max）经分析、归纳转化为混合模块TC2 CLA全面优化设计的结构参数约束.推导出TC2 CLA结构参数组位数jm,模块层数Mj与Nfanin（max）、Nfanout（max）的约束公式,并列出优化分析表.公式和优化表给出了TC2 CLA结构参数（jm、Mj）在全面优化设计中的约束,为混合模块TC2 CLA及优化序列、无等待时间序列的优化设计及操作位的扩展奠定了基础.     

基于逻辑结构的超前进位加法器的设计

通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。     

用于加法器的功耗延迟积优化混合进位算法

为了实现高性能的加法器,提出了面向功耗延迟积(PDP)优化的混合进位算法。该算法能快速搜索加法器的混合进位,以优化PDP。采用超前进位算法和行波进位算法交替混合,兼具超前进位算法速度快和行波进位算法功耗低的特点。该算法采用C语言实现并编译,结果应用于MCNC Benchmark电路,进行判定测试。与应用三种传统算法的加法器相比,应用该算法的加法器在位数为8位、16位、32位和64位时,PDP改进量分别为40.0%、70.6%、85.6%和92.9%。     

超前进位加法器的优化设计

在对超前加法器逻辑算法分析的基础上,介绍了一种优化设计方法。宽位加法器采用多层CLA（ Carry Look-ahead Adder）块技术,按四位为一组进行组间超前进位,减小硬件延时,达到并行、高速的目的。并在晶体管级重点对全加器进行优化设计,从而降低整个电路的延时、面积和功耗。仿真结果表明,在SMIC65 nm工艺下,设计出的16位超前进位加法器,其延时,面积,功耗相比传统结构都有了明显的改善,达到了优化的效果。     

64位超前进位对数加法器的设计与优化

设计一个应用于高性能微处理器的快速64位超前进位对数加法器.通过分析超前进位对数加法器原理,提出了改进四进制Kogge-Stone树算法的64位超前进位对数加法器结构,并结合使用多米诺动态逻辑、时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路.该加法器采用SMIC 0.18 μm CMOS工艺实现,在最坏情况下完成一次加法运算时间为486.1 ps,与相同工艺和相同电路结构采用静态CMOS实现相比,大大减少了加法器各级门的延迟时间,取得良好的电路性能.     

对数跳跃加法器的算法及结构设计

本文介绍一种新型加法器结构——对数跳跃加法器,该结构结合进位跳跃加法器和树形超前进位加法器算法,将跳跃进位分组内的进位链改成二叉树形超前进位结构,组内的路径延迟同操作数长度呈对数关系,因而结合了传统进位跳跃结构面积小、功耗低的特点和ELM树形CLA在速度方面的优势.在结构设计中应用Ling's算法设计进位结合结构,在不增加关键路径延迟的前提下,将初始进位嵌入到进位链.32位对数跳跃加法器的最大扇出为5,关键路径为8级逻辑门延迟,结构规整,易于集成.spectre电路仿真结果表明,在0.25μmCMOS工艺下,32位加法器的关键路径延迟为760ps,100MHz工作频率下功耗为5.2mW.     

一种超前进位加法器的新颖BIST架构

针对超前时进位加法器（CLA），提出了一种高效的BIST架构。这种新的架构结合了确定性测试和伪随机测试的优点，并避免了各自的短处。同时，还提出了一个测试向量集，并充分利用了CLA加法器内部结构的规整性，向量集规模较小，便于片内集成。最后，提出了一种计算特征值的新方法。     

Performance of DTN protocols in space communications

Delay/disruption tolerant networking (DTN) was developed to enable automated network communications despite the long link delay and frequent link disruptions that generally characterize space communications. The performance of DTN convergence layer adapter (CLA) protocols over asymmetric space communication channels has not yet been comprehensively characterized. In this paper, we present an experimental performance evaluation of DTN CLA protocols for reliable data transport over a space communication infrastructure involving asymmetric channel rates, with particular attention to the recently developed Licklider transmission protocol (LTP) CLA (i.e., LTPCL). The performance of LTPCL is evaluated in comparison with other two reliable CLAs, TCP CLA and a hybrid of TCP CLA and LTPCL, for long-delay cislunar communications in the presence of highly asymmetric channel rates. LTPCL is also evaluated and analyzed in a deep-space communication scenario characterized by a very long link delay and lengthy link disruptions.     

A Complex Variable Fractional-Delay FIR Filter Structure

This brief introduces a structure for complex variable fractional delay (FD) finite-length impulse response (FIR) filters. The structure is derived from a real variable FD FIR filter and is constituted by a set of fixed real linear-phase FIR filters and two multiply-accumulate chains containing variable multipliers. In this way the implementation complexity and delay may be reduced in comparison with the cascade approach which hitherto has been used for the same purpose. A design example is included to demonstrate the benefits of the new structure.     

一个标准化模块化的IP数据广播集成方案

IP数据广播技术在这几年里取得了长足的进展,但在标准化和模块化方面的建设却不多。基于近两年新技术的发展和新需求的出现,介绍了一个标准化、开放化、模块化的IP数据广播集成方案的设计、模块划分及模块之间的标准接口。可以预料标准化、模块化的IP数据广播将促进应用的进一步发展,并产生质的变化,如卫星广播网格。     

Joint estimation of interference frequency offset and time delay in PCMA system

For cooperative received high-order modulation PCMA (paired carrier multiple access) signals,joint estima-tion of frequency offset and time delay was proposed.The sequence samples stored locally were used as auxiliary data.Estimation of frequency offset and time delay was calculated by optimizing the objective function,which was obtained from the cross-correlation computation of the auxiliary data and mixed signal,and the optimized process was accom-plished by utilizing two-dimensional search.By setting the threshold of joint estimation,the calculated amount was greatly reduced.Modified Cramer-Rao bound (MCRB) of interference frequency offset and time delay was derived,which provided theoretical basis for performance of the proposed algorithm.Simulation results show that the algorithm has similar performance with existing algorithms,but its complexity is reduced by two-thirds.     

Fault Diagnosis with Imperfect Tests

This paper derives a minimum s-expected cost sequence of built-in-tests (BITs) which will partition modular equipment into mutually exclusive groups of modules. After a fault in the equipment, one of these groups will be identified by a BIT diagnostic subsystem as the group which contains a faulty module. The BITs are imperfect in the sense only that they might not detect all of the possible faults in the equipment; they are perfect in the sense that fault indications are never false. The proportion of faults detectable by each BIT is known. Both the cost of a BIT and the probability that a BIT will pass or fail are functions of which modules are tested. A recursive algorithm is developed which determines a sequence of BITs with a minimum s-expected life-cycle cost. The recursive algorithm is applied to a 4-element numerical example. The algorithm has neither been proved nor implemented for a computer.     

The Conro modules for reconfigurable robots

The goal of the Conro Project is to build deployable modular robots that can reconfigure into different shapes such as snakes or hexapods. Each Conro module is, itself, a robot and hence a Conro robot is actually a multirobot system. In this paper we present an overview of the Conro modules, the design approach, an overview of the mechanical and electrical systems and a discussion on size versus power requirement of the module. Each module is self-contained; it has its own processor, power supply, communication system, sensors and actuators. The modules, although self-contained, were designed to work in groups, as part of a large modular robot. We conclude the paper by describing some of the robots that we have built using the Conro modules and describing the miniature custom-made Conro camera as an example of the type of sensors that can be carried as payload by these robots.