实时监控系统中的数据通信校验及其实现方法

介绍了在实时监控系统中常用的几种数据通信校验方法及其特点;重点说明了循环冗余码(CRC)校验的原理、检错范围和实现循环冗余码校验的方法,并编制了相应的程序;还介绍了数据通信校验在卫星通信地球站监控系统中的应用。     

CRC校验在DALLAS单总线产品中的应用

通过对循环冗余校验（CRC）原理的分析,给出了CRC校验在DALLLAS单总线产品的硬件及软件中的实现方法。     

智能卡数据完整性校验

在智能卡的使用过程中,可能会由于某些原因破坏数据的完整性。这将影响到智能卡的正常使用,因此需要进行数据完整性校验。文中简述了异或校验和循环冗余校验的原理,结合智能卡的文件结构,提出了一种智能卡数据完整性校验的方法。     

循环冗余校验的实现方法

循环冗余校验在数字通信技术中有着广泛的应用。本文讨论了循环冗余校验的代数算法,并据此给出了软硬件的实现方法,供工程技术人员参考。     

CRC校验在计算机与S7-200 PLC通信中的设计与实现

详细介绍了循环冗余校验CRC（Cyclic Redundancy Check）的差错控制原理及其在工业控制中的上住机（计算机）和下住机（S7—200 PLC）中的实现。其中，上位机用VisualBasic 6．0编程，下住机用STEP7一Micro／Win编程，利用自由口通信方式来实现数据校验。本文中的系统具备实时显示、历史查询、系统暂停以及准确的信息循环冗余校验功能。     

基于FPGA的CRC编解码器实现

循环冗余校验(CRC)是一种广泛应用于通信领域以提高数据传输可靠性的差错控制方法。介绍了CRC码的原理,分析了CRC编码、解码电路设计思路。利用VHDL语言设计CRC(7,3)编解码器并通过QuartusⅡ仿真平台进行仿真验证,最后下载到FPGA芯片实现了CRC(7,3)编解码电路。仿真及实验结果表明采用此方法实现的CRC编解码器具有速度快、可靠性高及易于大规模集成的优点。     

循环冗余校验生成多项式的构造及其性能的理论分析

循环冗余校验CRC由于编码简单、检错能力强且误判概率低，是一种主要应用于二元码组的高效可靠的差错控制方法。首先分析了CRC的校验原理，进而构造了一个生成多项式，进行了性能的分析比较，最终提出了生成多项式的重要原则。     

通用并行CRC计算方法及FPGA实现

循环冗余校验(CRC)码是诸多信道编码方式中最常用的一种编码,也是一种检错概率高且容易硬件实现的检错码,因检错能力强、容易实现而得到广泛应用。首先,本文介绍了循环冗余校验的算法原理,分析了CRC校验码的具体运算过程;其次,本文在原算法的基础上提出一种高速并行CRC算法,并以CRC-CCITT为例,推导出8位并行运算的CRC-CCITT逻辑关系式;最后,本文根据推导的8位并行运算的逻辑关系式,描述了8位并行的CRC-CCITT硬件实现电路。将该算法与现有的查找表法的性能进行分析比较发现,该算法具有节省逻辑资源、运行速度快等特点。     

循环冗余检错码及其应用

介绍了循环冗余检错码的原理，主要给出了判断所校验的数据正确时余式为ｒ（ｘ）的证明过程，并且提出了一种简便的判断数据是否正确的方法。     

电力营销系统数据流循环冗余校验技术研究

为解决营销系统数据传输的误码以及数据类别混乱的问题，设计基于BP神经网络的电力营销系统数据流循环冗余校验技术。根据循环冗余原理获得循环冗余校验码，设置管理逻辑，引入BP神经网络，实现电力营销系统数据流循环冗余校验。实验结果显示：在可靠度阈值为1、高斯噪声信噪比为5.5dB的情况下，两个子系统与数据库之间数据传输平均比特差错率最低，且数据传输迭代时间更短，同时数据分类效果更为优异。     

一种基于分段CRC码级联Hash极化码的设计

极化码作为一种线性分组码，具有较低的编码复杂度和确定的构造，但当其为中短码长时，性能会有所降低。提出一种基于分段循环冗余校验（cyclic redundancy check，CRC）码级联Hash极化码的设计方法，该方法在原有Hash极化码（Hash-Polar）的基础上，采用CRC分段校验进行双校验，分段CRC码在译码过程中能辅助路径度量，即对译码路径进行修饰，以此提高路径选择的可靠性，提高性能；另外，分段校验是将校验码分散地添加到输入的信息序列中，译码时对于CRC不通过的情况，可提前终止译码路径以省去不必要的译码计算量。最后，译码结束时，Hash校验码对修饰后的L条路径进行校验，选出最佳译码路径。仿真结果表明，所提出的设计方法比 CRC 辅助的 Hash 极化码（Hash-CRC-Polar）误码性能更优异。在高斯信道下，当码长为 128 bit、码率为 1/2、误码率为 10^-3时，所提出的基于分段 CRC 校验码的 Hash 极化码比Hash-CRC-Polar获得了约0.25 dB的增益。     

RCPC码在数字集群系统中性能研究

数字集群系统语音信道编码的整体方案为CRC（循环冗余码）＋RCPC（速率兼容删除卷积码）＋交织，其中RCPC是一种纠错能力很强的差错控制编码方法，其解码深度也是影响数字集群信道编码纠错性能的重要因素。主要介绍RCPC的特点及具体编码过程，并通过计算机对不同差错保护方案及其译码深度进行了仿真。     

CRC-assisted error correction in a convolutionally coded system

In communication systems employing a serially concatenated cyclic redundancy check (CRC) code along with a convolutional code (CC), erroneous packets after CC decoding are usually discarded. The list Viterbi algorithm (LVA) and the iterative Viterbi algorithm (IVA) are two existing approaches capable of recovering erroneously decoded packets. We here employ a soft decoding algorithm for CC decoding, and introduce several schemes to identify error patterns using the posterior information from the CC soft decoding module. The resultant iterative decoding-detecting (IDD) algorithm improves error performance by iteratively updating the extrinsic information based on the CRC parity check matrix. Assuming errors only happen in unreliable bits characterized by small absolute values of the log-likelihood ratio (LLR), we also develop a partial IDD (P-IDD) alternative which exhibits comparable performance to IDD by updating only a subset of unreliable bits. We further derive a soft-decision syndrome decoding (SDSD) algorithm, which identifies error patterns from a set of binary linear equations derived from CRC syndrome equations. Being noniterative, SDSD is able to estimate error patterns directly from the decoder output. The packet error rate (PER) performance of SDSD is analyzed following the union bound approach on pairwise errors. Simulations indicate that both IDD and IVA are better tailored for single parity check (PC) codes than for CRC codes. SDSD outperforms both IDD and LVA with weak CC and strong CRC. Applicable to AWGN and flat fading channels, our algorithms can also be extended to turbo coded systems.     

基于公式递推法的可变计算位宽的循环冗余校验设计与实现

循环冗余校验(CRC)与信道编码的级联使用,可以有效改善译码的收敛特性。在新一代无线通信系统,如5G中,码长和码率都具有多样性。为了提高编译码分段长度可变的级联系统的译码效率,该文提出一种可变计算位宽的CRC并行算法。该算法在现有固定位宽并行算法的基础上,合并公式递推法中反馈数据与输入数据的并行计算,实现了一种高并行度的CRC校验架构,并且支持可变位宽的CRC计算。与现有的并行算法相比,合并算法节省了电路资源的开销,在位宽固定时,资源节约效果明显,同时在反馈时延上也有将近50%的优化;在位宽可变时,电路资源的使用情况也有相应的优化。     

维特比译码及其纠错能力的研究

在现代数字通信系统中,纠错编码技术的作用是很重要的,本文以卷积码为例,分析了纠错码的原理,并利用matlab实现了卷积码的编码和解码,对卷积码纠错原理进行了仿真研究。     

Low-Latency CRC Calculation in Turbo-Code Decoding

Design of Turbo-Code decoders for the 3GPP LTE/LTE-A standard focuses on achieving a high-throughput of up to 1 Gbps with low decoding latencies at very high code rates. At code rates close to one, as specified in LTE/LTE-A, the decoding process can oscillate. Although the decoder converges to a valid code word after half-iteration i, after half-iteration \(i+1\) the decoded code word is invalid again. To circumvent this, the CRC that is attached to each code word must be evaluated after each half-iteration. We present a generalized architecture for calculating the CRC On-the-fly during both non-interleaved and interleaved half-iterations and thus explicitly taking into account the requirements for low-latency Turbo-Code decoding. Further, we investigate the latency-, and energy savings provided by employing this calculation scheme. Lastly, we give post layout synthesis results for a case study implementation in state-of-the-art 28 nm FDSOI technology.     

适用于大气弱湍流信道的自适应码率极化码

为了提高光通信链路在大气弱湍流信道下的解码性能和传输效率,基于极化码的信息位嵌套特性,设计了一种自适应码率极化码。该码字在弱湍流信道中能充分地极化,纠错效果较好。为了调节码率,引入CRC校验码作为发送端的停止标志,逐次发送更低码率的码字直到译码结果通过校验,此时的码字码率即是保证可靠传输的最大码率。不同湍流强度下的仿真结果表明,在误帧率为10-8时,相比传统极化码,自适应码率极化码可以获得1.7~2.3 dB的性能增益。对自适应码率极化码的时延进行了仿真分析,并结合误帧率得到了自适应码率极化码的信息吞吐率,结果表明,在弱湍流信道中,自适应码率极化码的信息吞吐率能满足FSO的传输需求。     

An integrated error correction and detection system for digitalaudio broadcasting

Hybrid in-band on-channel digital audio broadcasting systems deliver digital audio signals in such a way that is backward compatible with existing analog FM transmission. We present a channel error correction and detection system that is well-suited for use with audio source coders, such as the so-called perceptual audio coder (PAC), that have error concealment/mitigation capabilities. Such error mitigation is quite beneficial for high quality audio signals. The proposed system involves an outer cyclic redundancy check (CRC) code that is concatenated with an inner convolutional code. The outer CRC code is used for error detection, providing flags to trigger the error mitigation routines of the audio decoder. The inner convolutional code consists of so-called complementary punctured-pair convolutional codes, which are specifically tailored to combat the unique adjacent channel interference characteristics of the FM band. We introduce a novel decoding method based on the so-called list Viterbi algorithm (LVA). This LVA-based decoding method, which may be viewed as a type of joint or integrated error correction and detection, exploits the concatenated structure of the channel code to provide enhanced decoding performance relative to decoding methods based on the conventional Viterbi algorithm (VA). We also present results of informal listening tests and other simulations on the Gaussian channel. These results include the preferred length of the outer CRC code for 96-kb/s audio coding and demonstrate that LVA-based decoding can significantly reduce the error flag rate relative to conventional VA-based decoding, resulting in dramatically improved decoded audio quality. Finally, we propose a number of methods for screening undetected errors in the audio domain     

一种基于增强奇偶校验码级联极化码的新型编译码方法

极化码作为一种纠错码,具有较好的编译码性能,已成为5G短码控制信道的标准编码方案。但在码长较短时,其性能不够优异。提出一种基于增强奇偶校验码级联极化码的新型编译码方法,在原有的奇偶校验位后设立增强校验位,对校验方程中信道可靠度较低的信息位进行双重校验,辅助奇偶校验码在译码过程中对路径进行修剪,以此提高路径选择的可靠性。仿真结果表明,在相同信道、相同码率码长下,本文提出的新型编译码方法比循环冗余校验(cyclic redundancy check,CRC)码级联极化码、奇偶校验(parity check,PC)码级联极化码误码性能更优异。在高斯信道下,当码长为128、码率为1/2、误码率为10-3时,本文提出的基于增强PC码级联的极化码比PC码级联的极化码获得了约0.3 dB增益,与CRC辅助的极化码相比获得了约0.4 dB增益。     

Multiple CRC-aided variable successive cancellation list decoder of polar codes

In order to change the path candidates, reduce the average list size, and make more paths pass cyclic redundancy check (CRC), multiple CRC-aided variable successive cancellation list (SCL) decoding algorithm is proposed. In the decoding algorithm, the whole unfrozen bits are divided into several parts and each part is concatenated with a corresponding CRC code, except the last part which is concatenated with a whole unfrozen CRC code. Each CRC detection is performed, and only those satisfying each part CRC become the path candidates. A variable list is setup for each part to reduce the time complexity. Variable list size is setup for each part to reduce the time complexity until one survival path in each part can pass its corresponding CRC. The results show that the proposed algorithm can reduce the average list size, and the frame error rate (FER) performance, and has a better performance with the increase of the part number.