VLSI可测性设计研究

从可测性设计与VLSI测试、VLSI设计之间的关系出发，将与可测性设计相关的VLSI测试方法学、设计方法学的内容有机地融合在一起。文中简要地介绍了VLSI可测性设计的理论基础和技术种类，简明地评述了可测性设计的现状和发展趋势，并且探讨了可测性设计的实现方法。     

VLSI CAD系统Electric的应用开发

本文介绍了VLSI计算机辅助设计系统Electric的功能和设计思想，说明了工艺文件的编制方法。通过应用开发，使该系统成为能在国内投入使用的VLSI设计系统。     

VLSI片上互连线电感提取技术及考虑电感效应的互连分析

VDSM工艺下，芯片的高速、高集成度趋使电磁耦合作用不容忽略；而电感效应的引入使VLSI设计和验证变得复杂，本文阐述了VLSI片上互连线电感提取技术现状及发展方向，对各类提取方法作了扼要比较；同时探讨了互连分析中包含电感效应时存在的部分问题和解决办法，以期作为提高VLSI设计、分析和验证效率的有效向导。     

一种VLSI设计到赋权超图的转换系统

本文基于VLSI划分问题的需要,提出了一种VLSI设计到赋权超图转换算法.该算法解决的关键问题是,它读取和遍历Verilog语言描述的树状结构VLSI设计,将其转换为赋权超图并存储为指定的文件存储格式,从而有效地将VLSI划分问题转换为超图划分优化问题.进而,本文给出了VLSI设计到赋权超图的转换系统（VLSI/Hypergraph Converter,VHC）的处理流程图,并在Windows平台下用C＋＋设计实现了VHC系统.实验及分析表明,该系统能正确地将Verilog语言描述的门级CPU测试用例转换为赋权超图,避免了直接在VLSI线网上进行划分,提高了VLSI划分的效率.     

多值逻辑在VLSI设计与测试中的若干应用

本文介绍了多值逻辑在VLSI设计与测试中的若干应用。包括可作为VLSI模拟、设计与分析工具的ECSA理论;改进VLSI可测试性设计的三值扫描设计;具有自校验性能的三中取二值逻辑系统以及基于三值逻辑的制入测试技术。这些多值逻辑技术为VLSI的设计与测试提供了新的工具与途径。     

基于CORDIC算法并行FFT设计与硬件实现

讨论了复杂128点FFT处理器的并行和旋转结构。VLSI实现FFT适用于超高速数据处理。随着新的VLSI技术的发展，高速处理和低功耗设计成为现实。使用CORDIC旋转处理器可以优化面积和速度的设计，在不降低数据处理速度的基础上，这种FFT仅仅使用了5．3万等效逻辑门。     

硅集成系统设计导论[四]

四、硅系统设计的CAD系统四(一)硅系统设计中CAD的主要内容如前所述,VLSI系统具有很高的复杂性.VLSI系统设计的关键是复杂性管理.硅系统的设计方法学的基本出发点即是有效的复杂性管理.为了实现硅系统的设计,必须开发建立在对应的设计方法学基础上的CAD系统.这种系统可以显著加快设计速度,可以在未进行实际制备前建立相应的模型对其功能及性能进行模拟,从而使设计一次成功的几率大为提高.根据VLSI的特点,通常芯片中一个错误就会使其失效.改正设计中的错误,需要重新设计,制版及流水制备,其代价十分昂贵.因此,CAD系统是VLSI设计中不可缺少的工具.随着复杂性的增大,CAD越来越成为VLSI设计的核心.     

Bresenham算法在VLSI设计中的应用

Bresenham算法是计算机图形学领域中使用最广泛的直线扫描转换算法，在多媒体显示芯片设计中可通过硬件实现其功能，对VGA芯片的速度和功能的提高有很大帮助。文章从VLSI设计的角度出发，详细介绍Bresnham算法在VGA芯片设计中的应用。     

CMOS VLSI设计技术

本文从电路组态,逻辑组态、匹配技术和设计方法上讨论了CMOS VLSI设计技术,以及如何实现高速低功耗和高门密度设计.     

印制电路与集成电路

Y99-61803 20020051999年第12届 VLSI 设计国际会议录=Proceedingsof the 12th international conference of VLSI design[会,英]/VLSI Society of India Department of Electronics,Government of India.—IEEE,1999.—642P,(EZ)报道了1999年1月7日至10日在印度 GOA 举行的第12届国际 VLSI 设计研讨会上的111篇文章。主要涉及 TCAD、ECAD、低功耗技术、测试技术、共同设计与综合、逻辑综合、多值逻辑、验证、DSP、模拟设计、物理设计、数字设计与应用等诸方面内容。     

低功耗VLSI芯片的设计方法

对便携式电子器件的日益需求已经导致了功耗在IC设计产业的重要性。根据VLSI的设计流程,结合微处理器的工作机制,在系统、行为、结构、逻辑和物理5个层面上对低功耗的设计方法做了全面地分析。     

A multi coding technique to reduce transition activity in VLSI circuits

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.     

VLSI Structures for Viterbi Receivers: Part II--Encoded MSK Modulation

As a specific application of the material presented in Part I, this companion paper identifies VLSI layout strategies for realizing correlative encoded MSK-type Viterbi receivers. When the source symbols are correlatively encoded using a first-order polynomial, the appropriate Viterbi receiver takes the form of a cube-connected cycle (CCC) structure. Second-order encoding polynomials give rise to a new type of area-efficient VLSI structure which is a generalization of the CCC structure. The results are important from two perspectives: 1) Isomorphisms between certain concepts in theoretical computer science and digital communications are established, and 2) good practical VLSI layouts are generated, by a structured design methodology, which commercial silicon foundries can fabricate.     

Low-power encodings for global communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling     

Design Examples of System Partitioning and Performance Allocation for VLSI Implementation

Generally, in the telecommunication industry, VLSI implementation is viewed as a means to cost reduction and is attempted only after successively decomposing a system into circuits corresponding to individual printed circuit boards (PCB's). This traditional "circuit-design" approach is unable to cope with and to exploit the potential of VLSI capabilities such as chip density and processing power. The availability of unprecedented processing power and the recognition of "effective endproduct cost" as the true measure for VLSI chip fabrication are leading the change over from integrated circuit design to integrated system design. In this paper, this emerging system design methodology for VLSI implementation and its two elements, system partitioning and performance specification allocation, are illustrated by two design examples; one relating to line-circuit design and the other to a packet-switch design.     

基于最小延迟限度的VLSI缓冲器功耗优化设计

本文在研究ＶＬＳＩ缓冲器优化设计中关于延迟和功耗的基础理论基础上,基于高性能ＶＬＳＩ系统的非线性特性,给出了关于优化缓冲器延迟,尺寸和功耗设计以及驱动负载之间的关系,给出了基于最小延迟限度,获取缓冲器最优功耗的设计方法,可使缓冲器性能明显提高。经ＳＰＩＣＥ模拟,说明设计模型和优化设计结果是可行和较理想的。     

Cellular-automata models for reliability analysis of systems onsilicon

Reliability issues are important during the design of VLSI integrated circuits built on silicon, due to several design constraints-higher performance and frequency, device miniaturization, higher levels of on-chip integration-that must be satisfied by the final product. Digital designs are usually subject to failures due to the increased operating temperature caused by their high power dissipation. This paper addresses the problem of analyzing the reliability with respect to power consumption of digital systems constructed with CMOS technology. The solution is simulation-based, and relies on a new, cellular automaton-based model which is particularly suitable for identifying the power characteristics of a sequential design. The model is discussed in detail; it provides a homogeneous representation of all the components of the circuit. Primary inputs, flip-flops, primary outputs, and their related cones of combinational logic are modeled in the same way by means of cellular automaton cells. The model is used to analyze reliability of sequential VLSI circuits. To prove the applicability of the model, we report experimental results on some standard benchmarks taken from the literature     

优化VLSI缓冲器功耗的设计模型研究

对优化超大规模集成（ＶＬＳＩ）缓立足点顺的功耗进行了研究,夺于驱动较大负载,在满足缓冲器延迟限度范围内实现系统功耗的最小化,是提高ＶＬＳＩ缓立足点顺性能的关键问题之一,文章发展了关于缓冲器信号延迟、功耗功间的关系,并给出了基于最小延 基础上缓立足点顺功耗的优化设计模型和方法。经ＳＰＩＣＥ模拟验证,该模型苛有效地降低系统功耗和提高系统工作性能,文章贪赃划合理和可行的。     

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits will be needed to extend circuit complexity to the range currently dominated by silicon