A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180 nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30 °C to +70 °C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15 °C to +0.35 °C. Similarly, CTAT generator has mean temperature accuracy of ±1 °C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18 mV/°C with the temperature inaccuracy of ±1.3 °C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5 °C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2 μW.     

A low-power rail-to-rail input-range linear delay element circuit

Delay elements are one of the key components in many time-domain circuits such as time-based analog-to-digital converters. In this paper, a new rail-to-rail current-starved delay element is proposed which not only presents good linearity for the voltage-delay curve over the input range of ground to supply voltage, but also it consumes a dynamic power only during the transition times without consuming any static power. The proposed delay element is designed and simulated in a 0.13-µm CMOS technology with a supply voltage of 1.2 V. Post-layout simulation results demonstrate that the proposed circuit has a linear voltage-delay transfer function with a voltage-to-time gain of −1.33 ps/mV. Moreover, when samples of a full-scale sin-wave input signal are applied to the proposed circuit with a clock frequency of 100 MHz, the power consumption is 30 µW, and signal-to-noise-and-distortion ratio (SNDR) of the output delay times is 30.4 dB, making it suitable for use in a time-based analog-to-digital converter with up to 5-bit resolution.     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques

A CMOS analogue current-mode multiplier/divider circuit is presented. It is based on a dynamic biasing applied at the bulk terminal of MOS transistors operating in both saturation and triode. With the proposed structure, the multiplier forms a feedback loop that improves the current swing and accuracy. The multiplier has been fabricated using a standard 0.18 µm CMOS technology. The circuit consumes 144 µW using a single supply voltage of 1.8 V with a measured THD lower than 1% for an output current of 38 µA, and requires a die area of 90 µm x 45 µm.     

Accurate operation of a CMOS integrated temperature sensor

A high-accuracy temperature sensor is designed by applying the temperature characteristics of substrate bipolar transistor in CMOS technology. Initial accuracy of the temperature sensor can be improved by chopper amplifiers and dynamic element matching. Using these two methods, the circuit realization of reference voltage is also described. Simulation results show that the inaccuracy is within×0.4 °C from ?40 to +100 °C. Experimental results, obtained from circuits fabricated in 0.5 μm CMOS process, indicate that the sensor is inaccurate within×0.7 °C from ?40 to +100 °C. The power dissipation is 0.35 mW and the chip area is 889 μm×620 μm. Compared with previously reported work, the temperature sensor in the paper has lower inaccuracy without calibration.     

Non-ohmic effect and pulse aging behavior of V/Mn/Co/Bi/Dy co-doped ZnO semiconducting varistors with sintering processing

We examined the effect of sintering on the microstructure, non-ohmic properties, clamping characteristics, and pulse aging behavior of V/Mn/Co/Bi/Dy codoped ZnO semiconducting varistors. The average grain size increased from 4.7 to 10.4 µm and the densities of the sintered pellets decreased from 5.47 to 5.37 g/cm³ with the increase in sintering temperature. The maximum non-ohmic coefficient (35.3) was obtained at a sintering temperature of 900 °C. Varistors sintered at 900 °C exhibited the best clamp characteristics, a clamp voltage ratio of 1.74–2.54 at a pulse current of 1–25 A. Varistors sintered at 925 °C exhibited the strongest electrical stability; variation rates for the breakdown field measured at 1.0 mA/cm², for the non-ohmic coefficient, and for the leakage current density were 3.4%, 6.6%, and −11.2%, respectively, after application of a pulse current of 100 A.     

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8  nW at 0.6 V supply. The active area is 0.019 mm².     

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm². This work has been successfully applied in 13-bit 200MSPS A/D converter.     

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm². The obtained average reference current is 6 nA having a slope of 5.5pA/°C.     

Investigation of n-ohmic contact of vertical GaN-based light-emitting diodes on graphite substrate with Ag-In bonding

Vertical light-emitting diodes (VLEDs) were successfully transferred from a GaN-based sapphire substrate to a graphite substrate by using low-temperature and cost-effective Ag-In bonding, followed by the removal of the sapphire substrate using a laser lift-off (LLO) technique. One reason for the high thermal stability of the AgIn bonding compounds is that both the bonding metals and Cr/Au n-ohmic contact metal are capable of surviving annealing temperatures in excess of 600 °C. Therefore, the annealing of n-ohmic contact was performed at temperatures of 400 °C and 500 °C for 1 min in ambient air by using the rapid thermal annealing (RTA) process. The performance of the n-ohmic contact metal in VLEDs on a graphite substrate was investigated in this study. As a result, the final fabricated VLEDs (chip size: 1000 µm×1000 µm) demonstrated excellent performance with an average output power of 538.64 mW and a low operating voltage of 3.21 V at 350 mA, which corresponds to an enhancement of 9.3% in the light output power and a reduction of 1.8% in the forward voltage compared to that without any n-ohmic contact treatment. This points to a high level of thermal stability and cost-effective Ag-In bonding, which is promising for application to VLED fabrication.     

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm².     

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm² with under 1 μW power consumption for providing 0.7 °C effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.     

A resistorless CMOS bandgap reference with low temperature coefficient and high PSRR

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35?µm CMOS process demonstrate that a temperature coefficient of 10.2?ppm/°C is realised with temperature ranging from ?40°C to 140°C, and a power supply rejection ratio of 58?dB is achieved with a maximum supply current of 27?µA. The active area of the presented BGR is 160?×?140?µm².     

A dual-loop shunt regulator using current-sensing feedback techniques

The dual-loop shunt regulator using current-sensing feedback techniques is proposed in this paper. This architecture adopts a voltage and current loops to increase the transient response of the proposed shunt regulator. The maximum output current of the proposed shunt regulator is 180 mA at a 1.8 V output. Moreover the architecture of the proposed shunt regulator can suppress the stray effect which is from power supply. The prototype of the proposed shunt regulator is fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-μm CMOS 2P4M process. The active area is only 579×355 μm².     

A new CMOS differential current-mode AGC on the division operation based

A new CMOS differential current-mode AGC on the division operation based is presented. The operation principle consists in detection of both positive and negative envelopes of the differential input signal cycles, respectively. The output signal with constant magnitude is obtained by dividing the differential input signal to the difference between the positive and negative detected envelopes. The new current-mode architecture of the proposed AGC (composed only by an envelope detector and a divider stage) diminishes significantly the settling time, the circuit complexity and the power consumption. The circuit yields an input dynamic range of 15 dB and provides a constant magnitude output signal in the frequency range from 10 MHz to 70 MHz. The current consumption is 5 mA from a single 3.3 V supply voltage. The simulations performed in 0.13 µm CMOS process confirm the theoretically obtained results.     

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65 nm CMOS process and achieves a measured saturated output power of 10.61 dBm and a peak power added efficiency of 8.13% at 73 GHz with only 1 V power supply. The die area including pads is 1.23×0.45 mm², while the power combiner only occupies 200×80 μm².