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1.
A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(read current ratio of 10~4×),low process variation,good thermal reliability and available retention time(190 ms).Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.  相似文献   

2.
Threshold current characteristics of intracavity-contacted oxide-confined vertical-cavity surface-emitting laser had been investigated in detail. Threshold current characteristics not only were depended on the size of oxide-aperture, but also were also strongly affected by the mismatch of its lasing mode and gain peak. For the same degree detuning of the gain peak and lasing mode at room temperature, the threshold current was approximately proportional to the square of the oxide-aperture diameter of above 5μm. For the same oxide-aperture device, the larger the detuning degree of the lasing mode shifted to the shorter wavelength of the gain peak at room temperature was, the lower the minimum threshold current was. The wavelengths of the lasing mode and gain peak were ±N×10nm detuning at 300K, The temperature of the minimum threshold current was changed to be about ±N×40K(N real number). The calculated results were consistent with the experimental ones.  相似文献   

3.
The growth front evolution of GaN thin films deposited on sapphire substrate by hydride vapor phase epitaxity has been studied with atomic force microscope. The evolution of the surface morphology presents four features of stage with the growth process. In initial growth stage, the surface is granular, and the typical grain diameter is about 250nm for t =0.1min. 3D growth plays a key role before the films come up to full coalescence, which causes a rough surface. After 0.1min the growth dimension decreases with the increase of lateral over growth, the surface roughness obviously decreases. From 0.4min to 3min, the growth front roughness increases gradually, and the evolution of the surface roughness exhibits the characteristics of self-affined fractal. Beyond 3min, the root-mean-square decreases gradually, which means the deposition behavior from hyper-2D growth gradually turns into layer growth mode with the increase of growth time.  相似文献   

4.
The investigations on Ge-implanted GaN films grown by MOCVD and then annealed at 1100℃ under ammonia ambient have been carried out. With increasing Ge implantation dose, four additional peaks arise at wave numbers of 260, 314, 428 and 670cm-1 in Ramam spectra. In PL spectra, the relative intensity of the band-edge emission compared to the PL-band centered at 2.66eV and the yellow band decreases with increase of Ge-implanted dose. The modes of 260 and 314cm-1 are attributed to disorder-activated Raman scattering, whereas the modes of 428 and 670cm-1 are assigned to local vibrations of vacancies and vacancy-related complexes. The PL-band centered at 2.66eV and the yellow band is also related to these vacancy defects. The new Raman peak at 301cm-1 for the sample annealed only 5min originates from Ge clusters due to deficient annealing.  相似文献   

5.
All-optical switching has been theoretically analyzed in the 3,3'-diethyl-2,2'-thiatricarboeyanine iodide (DTTCI) carbocyanine dye that exhibits large excited-state absorption to achieve high contrast and fast switching. Switching has been analyzed both ns and ps pump pulse widths. It is shown that there is an optimum value of concentration for given peak pump intensity at which maximum modulation can be achieved. We can get 93.84% modulation of transmission of a CW probe laser beam at 532 nm at peak pumping intensity of 500 kW/cm^2 at 763 nm, with At =1 ns and concentration of 80 μM in alcohol, resulting in switch-off and on time of 2 ns and 8 ns, respectively. The results have been also used to design all-optical NOT and the universal NOR and NAND logic gates with multiple pump laser pulses.  相似文献   

6.
Printing of metal bottom back electrodes of flexible organic solar cells (FOSCs) at low temperature is of great significance to realize the full-solution fabrication technology.However,this has been difficult to achieve because often the interfacial properties of those printed electrodes,including conductivity,roughness,work function,optical and mechanical flexibility,cannot meet the device requirement at the same time.In this work,we fabricate printed Ag and Cu bottom back cathodes by a low-temperature solution technique named polymer-assisted metal deposition (PAMD) on flexible PET substrates.Branched polyethylenimine (PEI) and ZnO thin films are used as the interface modification layers (IMLs) of these cathodes.Detailed experimental studies on the electrical,mechanical,and morphological properties,and simulation study on the optical properties of these IMLs are carried out to understand and optimize the interface of printed cathodes.We demonstrate that the highest power conversion efficiency over 3.0% can be achieved from a full-solution processed OFSC with the device structure being PAMDAg/PEI/P3HT:PC61BM/PH1000.This device also acquires remarkable stability upon repeating bending tests.  相似文献   

7.
Field Programmable Gate Array (FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing mieroehip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system inte- gration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, intercon- nects, and embedded resources. Moreover, some important emerging design issues of FPGA archi- tectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.  相似文献   

8.
An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 μm and 0.7 μm are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively.  相似文献   

9.
The influence of shallow trench isolation (STI) on a 90 nm polysilicon–oxide–nitride–oxide–silicon structure non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.  相似文献   

10.
In this paper, an attempt has been made to give a detailed review of strained silicon technology. Various device models have been studied in this paper that consider the effect of strain on the devices and their comparisons have been drawn. A review of some modeling issues in strained silicon technology has also been outlined. The review indicates that this technology is very much required in nanoscale MOSFETs due to its several potential benefits and there is a strong need of an analytical model which describes the complete physics of the strain technology.  相似文献   

11.
In this paper, we extensively investigated the structure and electrical characteristics of an n-type poly-Si thin-film transistor with a novel 3D fin-like channel. Further, owing to the high-quality thin film in the channel, an experimental device with a nonvolatile (NV) memory structure for system integration on panel or embedded memory applications is successfully demonstrated for the first time. By following the previously reported method and by improving the process conditions, the final fin-like channel shows a real 3D profile and a maximum aspect ratio of 3.5:1 with a minimum average width equal to 135 nm after an excimer laser annealing on a unique prepatterned amorphous silicon channel. The high-level dc characteristics, such as carrier's field-effect mobility up to 289 cm2 /V.s, subthreshold slope below 190 mV/dec, ON-OFF current ratio greater than 5 x 106, etc., reveal the effect of film quality and the advantage of the gate-all-around structure on the device's performance; moreover, it also indicates one potential scaling method for this technology. By applying a special program/erase (P/E) mode with electron injection/expulsion from the backside gate electrode, the NV memory structure in this channel demonstrates reasonable P/E characteristics, threshold voltage shifting of 1.41 V at | Vg = 12 V, pulse time = 1 ms, and acceptable reliability.  相似文献   

12.
A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature  相似文献   

13.
In these days, the researches of non-volatile memory device using nano-crystal(NC)-Si are actively progressing to replace flash memory devices. Many kinds of non-volatile memory devices such as phase-change(P)-RAM, resistance(Re)-RAM, polymer(Po)-RAM, and nano-floating gate memory(NFGM) are being studied. In this work, we study NFGM device in which information is memorized by storing electrons in silicon nanocrystal. The NFGM device has shown great promise for ultra-dense high-endurance memory device for low-power applications [S. Tiwari, et al., Appl. Phys. Lett. 68 (1996) 1377], and it is able to fabricate 1T-type device. Thus, the NFGM is considered to replace existing flash memory device. Non-volatile memory device has been fabricated by using NC-Si particles. The NC-Si particles have broad size range of 1-5 nm and an average size of 2.7 nm, which are sufficiently small to indicate the quantum effect for silicon. The memory window has been analyzed by C-V characteristic of NC-Si particles. Vd-Id and Vg-Id characteristics of the fabricated device have also been measured.  相似文献   

14.
The purpose of this work is to investigate the effect of device size and frequency on memristor based Resistive Random Access Memory (RRAM). The objects of investigation are effect on memory window, Low Resistance State (LRS) and High Resistance State (HRS) with memristor device size varied from 5 nm to 50 nm. Moreover, effect of device size variation on lifetime (τ) reliability of memristor device has also been explored. The results evidences that, memristor possess higher memory window and lifetime (τ) in the lower device size with lower frequencies. This subsequently consequences into lower data losses in the overall memory architecture having memristors as the basic building block. Authors have analysed effective variation in LRS and HRS by accomplishing Monte-Carlo simulation. The results of Monte-Carlo simulation suggests the LRS to follow Weibull distribution whereas HRS to go along with Gaussian distribution for less read and write errors.  相似文献   

15.
3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.  相似文献   

16.
An out-of-plane guided-mode resonance filter on a single Si chip using a two-layer polysilicon surface micromachining process has been proposed. To the best of the authors' knowledge, this is the first time that a monolithic optical filter has been integrated on a silicon micro-optical bench. This device can be used as a bi-directional transceiver filter. The extinction ratio between 1550 and 1310 nm could be as low as 40 dB and the channel passband at 1550 nm was 20 nm.  相似文献   

17.
A special device with photocurrent amplification function is reported.The device with long base region structure consists of dual-route photodetectors and their amplifier.Two photodetectors with a space of 50μm are precisely located in this device.The dvice with current snesitivity of S≥ 15A/lm,static state current transmission coefficient of hFE≥5000,single-route dark current of ID≥1μA,high frequency current transmission coefficient modulus of |hfe|≥1 at 400MHz is obtained.At present,the device has been tried out in some inertia systems.  相似文献   

18.
A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultra-low supply voltage operation also in CMOS processes with high threshold voltages. This paper presents the theoretical basis for the design of VT0n = | VT0p | = 0.9VV_{T0n} = \left| {V_{T0p} } \right| = 0.9V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than ±18 A with a supply voltage down to 1 V, and relatively small device dimensions. In spite of the relatively large signal processing range, the class AB operation of the cell enabled a very low quiescent current consumption, 1 A in this design, resulting in a very high current efficiency and effective power consumption, as well as good noise performance.  相似文献   

19.
P-channel MOSFETs stressed at a given drain voltage over the entire range of device saturation, 0 V⩽|VG|⩽|VD |, are discussed. Two different gate currents of opposite polarity were observed. These gate currents are shown to be correlated with device degradation behavior, which is distinctly different in each case. The gate bias thus divides into two stress regions, corresponding to small and large |VG|. In the former, the parameter shift is initially pronounced but saturates in time. In the latter, the device degradation is initially small but cumulative in time. Therefore, both stress regions are equally important in affecting the device lifetime. A phenomenological model of gate current to support the two-region gate stress model is presented  相似文献   

20.
A nanoscale nonvolatile memory device made from RbAg4I5 solid electrolyte has been made directly on a Si substrate with lateral size scaled down to 100 nm. By applying voltages with different polarity, the device could be switched between high- and low-resistance states. The ratio between the high and low resistances could reach ∼103, and the low-resistance state showed rectifying diode characteristics. The configured resistances remained nonvolatile after switching, and the device could be switched repeatedly for ∼103 times. Our results show that the nanoscale nonvolatile memory device can be integrated directly with Si-based circuit and can be potentially used for high-density memory application.  相似文献   

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