FPGA signal processing using sigma-delta modulation

FPGA devices maintain the flexibility of software-based solutions, while providing levels of performance that match, and often exceed ASIC solutions. There is a rich and expanding body of literature devoted to the efficient and effective implementation of digital signal processors using FPGA-based hardware. More often than not, the most successful of these techniques involves a paradigm shift away from the methods that provide good solutions in software programmable DSP systems. This article reports on the rich set of design opportunities that are available to the signal processing system designer through innovative combinations of ΣΔ modulation techniques and FPGA signal processing hardware. The applications considered include narrow-band filters, both single-rate and multi-rate; DC canceller; and ΣΔ modulation hybrid digital-analog control loops for simplifying carrier recovery, timing recovery, automatic gain control (AGC) loops in a digital communication receiver     

Implementation of the Longstaff and Schwartz American Option Pricing Model on FPGA

American style options are widely used financial products, whose pricing is a challenging problem due to their path dependency characteristic. Finite difference methods and tree-based methods can be used for American option pricing. However, the major drawback of these methods is that they can often only handle one or two sources of uncertainty; for more state variables they become computationally prohibitive, with computation times typically increasing exponentially with the number of state variables. Alternative solutions are the extended Monte Carlo methods, such as the Least-Squares Monte Carlo (LSMC) method suggested by Longstaff and Schwartz, which uses of regression to estimate continuation values from simulated paths. In this paper, we present an FPGA hardware architecture for the acceleration of the LSMC method, with Quasi-Monte Carlo path generation. Our FPGA hardware implementation on a Xilinx Virtex-4 XC4VFX100 chip achieves 25× and 18× speed-ups in the path generation and regression steps, respectively, compared to an equivalent pure software implementation captured in C++ and run on an Intel Xeon 2.8 GHz CPU. This provides overall speed-up of 20× compared to a CPU-based implementation. Power measurements also show that our FPGA implementation is 54× more energy efficient than the pure software implementation.     

基于神经网络的红外目标分类算法设计与应用

卷积神经网络在图像处理领域取得了突出表现，但是由于算法庞大的计算量引起功耗高和实时性差的问题导致神经网络的实际应用受到一定限制。如果将神经网络移植在FPGA硬件平台，可充分发挥其高度并行的优势实现网络加速，降低功耗并提升算法实时性。基于上述描述，本文将用于目标分类的网络模型成功移植在FPGA上，通过对比加入分类模型前后的告警结果，说明分类模型设计的重要性。对比硬件实现与仿真结果，证明硬件实现的正确性。     

Design of an Embedded Arabic Optical Character Recognition

This work presents an embedded Arabic OCR system. The proposed system is compact and portable which make it useful for many applications such as blind assistance and language translation. OCR system consists of the sub-systems: image acquisition, pre-processing, segmentation, feature extraction, classification, and post- processing. For each sub-system there are several of algorithms and techniques to be implemented. Working with PCs gives the designer freedom to select the algorithms and techniques according to the required performance, reliability and reusability. However with the embedded systems we are facing many problems and challenges. Such challenges are associated with memory, speed, and computational power. FPGA is selected as the hardware platform for realizing that recognition task. An OCR system is designed and implemented on PC. Then this system is transferred to FPGA after a set of optimization procedures. Utilizing the features of FPGA technology, Hardware / Software co-design is accomplished on an FPGA board. In that design the systems is partitioned into software modules and hardware components to get the advantages of software flexibility and hardware speed. A database of 3000 Arabic characters is used to train and test the performance of the system. The effects of changing the number of features and classification parameters on accuracy, memory and speed are measured. Design points are selected in order to improve the memory required, speed and computation power without affecting the accuracy.     

An Efficient FPGA Implementation for 2-D MUSIC Algorithm

Multiple signal classification (MUSIC) algorithm is widely used in measuring the direction of arrival. In VLSI implementation of a two-dimensional MUSIC algorithm, the two primary modules, eigenvalue decomposition and spatial spectrum search, generally consume a significant hardware and cause long processing delay. Two novel design techniques: serial rotation angle broadcasting and multi-scale peak searching are introduced in this paper to mitigate these problems. An FPGA implementation is presented to demonstrate the efficiency of the proposed techniques. It only takes 1 ms for one set of 2-D direction estimation, and the deviations in elevation angle and azimuthal angle are both less than \(0.1^{\circ }\). The whole design is implemented in Xilinx’s Virtex-6 LX130T, which consumes about 60 % of the total resources of a single device.     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration     

RAPID PROTOTYPING - Area efficient FIR filters for high speed FPGA implementation

A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm     

WLAN SOC芯片BX501的FPGA验证平台设计与实现

系统芯片（SOC）设计是以模块复用和软硬件协同设计为基础，基于FPGA的验证平台是一种有效的验证途径。文章讨论了WLANSOC芯片BX501的验证平台的两种实现方案，介绍了采用Xilinx Virtex-Ⅱ系列FPGA的设计实现；同时对SOC设计的FPGA验证问题进行了分析和探讨。     

一种QPSK突发信号的信噪比估计方法

介绍了几种信噪比的估计方法,对这些估计方法的性能做了比较,得到了一种适合于QPSK突发信号信噪比估计的方法,并介绍了其FPGA实现。所采用的信噪比估计方法利用训练序列的相关峰值和能量值进行运算,从而得到估计的信噪比。通过MATLAB仿真和硬件实现表明,利用较短的训练序列就可以得到范围较宽、准确度较高的信噪比估计值,其应用可扩展到其他类似突发通信系统中。     

Viterbi译码器回溯算法实现研究

该文介绍了两种Viterbi译码器回溯译码算法,通过对这两种算法硬件实现结构上的优化,给出了这两种算法的FPGA实现方法,比较了两种实现方法的优缺点。最后将其应用在实际的Viterbi译码器设计上,验证了算法实现的正确性。     

High performance VLSI architecture for block based visible image watermarking

In this article, a novel block-based visible image watermark VLSI architecture design and its hardware implementation in field programmable gate array (FPGA) is proposed. In this watermarking process, 1D-DCT is introduced to facilitate hardware implementation. Mathematical model is developed to reduce the computational complexity for the calculation of embedding and scaling factors, which are used to make the resultant image of best quality with uniform watermark visibility. The proposed architecture has a 12–stage pipeline. Parallelism techniques are employed in block level in order to achieve high performance. A single 8-point fast 1D-DCT is used to calculate the DCT coefficient values of the host image and the watermark image to minimize the resource utilization and power consumption. The hardware implementation of this algorithm leads to numerous advantages including reduced power, area and higher pipeline throughput. The performance of the architecture is studied by implementing Xilinx Virtex V technology based FPGA with DSP 48E. Throughput achieved based on this VLSI architecture is 5.21 Gbits/s with a total resource utilization of 4058BELs.     

OFDM系统的研究及软件无线电实现

OFDM系统有直接实现和DSP实现2种方法。在分析OFDM系统时发现,采用DFT方法处理OFDM不仅大大简化调制解调器的设计,而且可以在DSP芯片和硬件结构中快速实现FFT计算,因此在考虑OFDM系统的调制解调原理、系统采取的抗干扰能力的举措、利用DSP技术和FFT快速算法的基础上,设计了一个以DSP和FPGA为核心的实现OFDM发送、接收系统的方案。     

Modeling and Hardware Implementation Aspects of Fading Channel Simulators

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. Two major approaches have been widely used to produce statistically accurate fading variates, namely shaping the flat spectrum of Gaussian variates using digital filters and sum-of-sinusoids (SOS)-based methods. Efficient design and implementation techniques for these schemes are of particular importance in the design and verification of wireless systems with a relatively large number of channels, such as ad hoc networks. This paper considers the modeling and implementation aspects of fading channel simulators. First, we present a novel computationally efficient implementation of a filter-based fading channel simulator on a single field-programmable gate array (FPGA) device. The new technique significantly alleviates the challenges of real-world testing of communication systems by introducing a fast and area-efficient FPGA implementation of the fading channel. Our fixed-point implementation of a Rayleigh-fading channel simulator on an FPGA utilizes only 3% of the configurable slices, 10% of the dedicated multipliers, and 1% of the available memories on a Xilinx Virtex-II Pro XC2VP100-6 FPGA, while the simulator operates 12.5 times faster than the example sample rate. Then, we describe a compact implementation of the SOS-based fading simulator that uses only 1% of the configurable slices and 1% of the available memories on the same FPGA device while generating over 200 million complex Rayleigh-fading variates per second.     

直接序列扩频系统中伪码同步的FPGA实现

针对直接序列扩频(DS-SS)系统中,需要精确伪码(PN码)同步这一难题,给出了一个基于FPGA的实现方案,并对其进行了时序仿真及和硬件调试,结果表明电路工作正确可靠,能满足设计要求.     

Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications     

基于FPGA的QPSK高速解调器的设计与实现

根据无人机系统对数据链路的高速率、低误码的需求,分析比较了QPSK数字中频解调与零中频解调2种方案。针对本系统的特点,采用FPGA及DSP设计实现了一种高速QPSK数字零中频解调器,同时简要分析了高速数字解调器的工作原理,并介绍了高速解调器的硬件与软件实现。     

一种基于FPGA的群路信号数字分路实现结构

研究了一种基于FPGA实现的群路信号数字分路实现结构。文中对分路算法进行数学推导,然后给出了FPGA实现结构,并在硬件平台上进行了验证。其结果表明,该结构能有效降低FPGA的硬件资源消耗,在全数字群解调器中有着良好地应用前景。     

基于FFT的校频技术及其FPGA实现

在全数字化MPSK(多相移键控)解调中,有时存在着相当大的相对载波频偏,导致接收机不能正常工作.文中介绍了基于最大似然准则的FFT(快速傅里叶变换)频偏估计算法,分析了该算法的复杂度,并将该算法应用于MPSK信号载波恢复,达到对频偏进行有效估计并矫正的目的.首先给出了应用FFT频率估计器的MPSK信号载波恢复结构,以及在FPGA(现场可编程门阵列)上实现该算法的关键技术.在使用IP核的基础上,详细描述了FFT频率估计器在FPGA中的实现过程.最后分析了算法实现时需要的硬件资源和性能.