A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

Fast modeling of core switching noise on distributed LRC power gridin ULSI circuits

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0±5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted     

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 μm, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e ^2.3(≈10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e^1.6(≈5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants     

A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits

A compact add-on model is proposed to simulate the mechanism of charge trapping and release (detrapping) and its effect on the threshold voltage of MOSFET devices. The model uses implicit algebraic differential equations compatible with transient analysis in SPICE. It also shares the accuracy level of the transient analysis. A micro-model approach is used, and each trap is treated by a two-state Markov process. The normalization of trap behavior can be enabled or disabled, so that the designer can compare average trap behavior to the result of repeated Monte-Carlo simulations of a circuit. In this manner, the model can compromise between device-level modeling and circuit-level modeling. Unlike models geared towards digital circuit design, the trapping and release rates need not be constant during electrical stress. The trapping and release rates are a function of time, as they depend on the circuit state-space equations. An operational amplifier is analyzed using the new model, and the proposed approach is compared with the state of the art.     

Analog circuit sizing via swarm intelligence

Together with the increase in electronic circuit complexity, the design and optimization processes have to be automated with high accuracy. Predicting and improving the design quality in terms of performance, robustness and cost is the central concern of electronic design automation. Generally, optimization is a very difficult and time consuming task including many conflicting criteria and a wide range of design parameters. Particle swarm optimization (PSO) was introduced as an efficient method for exploring the search space and handling constrained optimization problems. In this work, PSO has been utilized for accommodating required functionalities and performance specifications considering optimal sizing of analog integrated circuits with high optimization ability in short computational time. PSO based design results are verified with SPICE simulations and compared to previous studies.     

A dynamic CMOS multiplier for analog VLSI based on exponentialpulse-decay modulation

A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients     

电流模电路的通用单元电路

提出了电流模电路中的一个通用积木块－伴随运放。用它能把基于电压运放的电压模电路转换成电流模电路。分析了理想伴随运放的特点和应用,提出一种ＣＭＯＳ伴随运放电路,介绍了用它设计的电流模滤波器。     

一种用于AC/DC控制器中电压基准源的设计

提出了一种新颖的可用于AC/DC控制芯片中的基准电压源电路。此电路以PTAT（proportional to absolutetemperature）电流为偏置电流,利用二极管连接的MOS晶体管迁移率和阈值电压的温度系数可相互补偿的特性,产生与温度无关的栅源电压。该电路结构简单,既无启动电路也无运放,避免了运放失调对基准源的影响,设计采用CSMC0.5μm BCD工艺。仿真结果表明,该基准电压源具有较低的温度系数和高电源电压抑制比,可作为AC/DC控制芯片中迟滞比较器的参考源。     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. Both the coefficient set as well as the exponent set of the posynomial expression, for some performance as a function of the design variables, are determined based on performance data extracted from SPICE simulation results with device-level accuracy. Techniques from design of experiments (DOE) are used to generate an optimal set of sample points to fit the models. We will prove that the optimization problem formulated for this problem typically corresponds to a non-convex problem, but has no local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that can be used to compose a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities of the presented modeling technique.     

On the generation of CCII and ICCII oscillators from three Op Amps oscillator

A new quadrature oscillator using two current conveyors (CCII) and two inverting current conveyors (ICCII) is generated from a three Op Amp two integrator loop oscillator. The proposed oscillator is generalized and it is found that it is a member of a family of 64 oscillator circuits using combination of CCII and ICCII. Four of the reported oscillators are floating. The three Op Amps oscillator is also found to be the reference oscillator circuit in the generation of two basic CCII two integrator loop grounded passive element oscillators. The nodal admittance matrix (NAM) expansion is used to show the basic steps in the generation of the two alternatives CCII grounded passive element oscillators. Each of the two CCII oscillators is a member of a family of sixteen oscillator circuits using combination of CCII and ICCII. Two of the reported oscillators are floating and their adjoint oscillator circuits are not floating. Simulation results are included.     

Design and implementation of OTA based fractional-order oscillator

This paper deals with design and implementation of fractional-order (FO) oscillator based upon two topologies which employ operational transconductance amplifier (OTA). The first topology is developed on a trans-admittance mode fractional-order all-pass filter (FAPF) cascaded with an trans-impedance mode integrator whereas the other one consist of a trans-admittance mode FAPF cascaded with a trans-impedance mode differentiator. The presence of OTA makes the proposed FO oscillator electronic tunable. Both topologies are verified through SPICE simulations using 180nm CMOS technology node. The ability of proposed FO oscillator, to generate very low frequency is also explored in this work. The stability analysis is done using forlocus function of MATLAB and the mathematical equations for sensitivity of the oscillation frequency with respect to various circuit parameters are also derived. Further, to ensure the robustness of the proposed circuits process-voltage-temperature (PVT) and Monte Carlo analyses have been performed.

     

具有容错能力的波长路由光网络的拓扑设计

研究了具有容错能力的波长路由光网络的拓扑设计问题.提出了一种基于业务流的初始物理拓扑产生算法,与随机拓扑生成算法相比,该算法产生的物理拓扑更接近于最优拓扑.另外,还提出了一种新的链路拥塞计算方法,它能够更好地反应链路的实际状态.数值结果显示文章提出的物理拓扑设计策略具有更快的收敛速度.     

Design of inverse class-E amplifier with finite D.C. feed inductance

This paper reports on a design of inverse class-E amplifier with finite D.C. feed inductance. The finite D.C. feed inductance is resonated by the parallel capacitance at the fundamental frequency. The direct design equations required to determine the optimum operations are derived in detail. Comparing with the classic inverse class-E amplifier, numerical results show that improvements in minimizing size, cost, and complexity of the circuit can be obtained by the inverse class-E topology with finite D.C. feed inductance. Comparing with the sub-harmonic and parallel-circuit class-E amplifiers, the inverse class-E topology with finite D.C. feed offers advantages for MMIC realization. Theoretical analysis is validated by numerical simulation and measurement. Excellent agreement between theory and simulation results is achieved. Comparison between simulations and measurements of an experimental circuit validate the feasibility of the design. A measured output power of 40.01 dBm, with a drain efficiency of 80.16% and power-added efficiency of 78.93% were obtained at 250 MHz with a 22-dBm input power.     

感性脉冲电流注入装置的SPICE电路建模

为预测电子设备传导敏感度试验中脉冲电流注入在设备端口产生的干扰强度及波形,建立了感性电流注入装置的SPICE(Simulation Program with Integrated Circuit Emphasis)电路模型.在将装置电路模块化的基础上,应用传输矩阵计算的方法,从实验数据中提取出各模块的电路参数或方程表达式,并转换为SPICE模型,最后再将各模块组合为完整的装置模型.频域和时域的实验显示,模拟结果和测量结果一致性较好.建立的电路模型可用于设计和优化脉冲电流注入试验.     

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.     

An efficient method for finding DC solutions for Josephson circuits

The formulation of Josephson circuit equations in the DC state is discussed and a mixed-mode approach that combines the nonlinear solution method of source-stepping and time-domain method of numerical integration is proposed. Since Josephson circuit equations are often multivalued, the mixed-mode algorithm follows the paths of the independent sources, detects ill-conditioned points, and converges to stable points on the characteristic curves of the simulated circuit. The algorithm uses a combination of source stepping and transient calculation with resistive damping. An adaption of method to superconducting quantum interference device (SQUID) threshold curve calculation is also discussed. The techniques are suitable and presented in sufficient detail, so that a reader may implement them as part of a general simulation program such as JSIM or SPICE     

The Combinational and Sequential Adiabatic Circuit Design and Its Applications

In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 μm MOSIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal power-clock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20–30 fJ and 70 fJ energy consumption at 10–100 MHz and 500 MHz operating frequency, respectively.