卷积LDPC码流水线译码器的改进方法

较高的译码复杂度和较长的初始译码时延是卷积LDPC码流水线译码器两个潜在的问题。本文提出一种通过在计算校验节点信息时引入乘积因子的方法降低各节点信息之间的相关性,从而提高译码效率,一定程度上降低了译码迭代次数。仿真结果表明,该译码算法缩短了译码器的初始时延,同时也降低了译码复杂度,从而使得译码器的性能得到改善。     

基于多元LDPC码扩展最小和译码的软信息迭代生成算法

为克服多元LDPC码的扩展最小和(Extended Min-Sum, EMS)译码算法中对数似然比(Log Likelihood Ratio, LLR)生成及排序复杂度过高的问题,该文针对以BPSK为调制方式的编码调制系统,提出一种快速而简单的LLR生成算法。该算法采用一种低复杂度的迭代计算方式,可快速生成并排序LLR,适用于硬件实现的流水线结构,能够加速译码器的译码速度并提高译码器吞吐量。仿真结果表明:所提出算法对译码性能基本没有影响且极大降低LLR计算的复杂度,是一种适用于高速多元LDPC译码器前端实现的候选算法。     

三维TPC译码器的设计及FPGA实现

Turbo乘积码（TPC）是一种性能优秀的纠错编码方法,它具有译码复杂度低、译码延时小等优点,且在低信噪比下可以获得近似最优的性能。介绍了基于Chase算法的三维TPC软输入软输出（SISO）迭代译码算法,提出了三维TPC译码器硬件设计方案并在FPGA芯片上进行了仿真和验证。测试结果表明,该译码器具有较高的纠错能力,满足移动通信误码率的要求。     

并行级联分组码的一种新的迭代译码算法

并行级联分组码比串行级联分组码具有更高的码率,基于LLR计算的Turbo迭代译码算法使其内外分量码均做到了软判决译码。通过引入校正因子a（m）,将接收信息与子译码器的输出软信息进行线性叠加反馈能在省去繁琐的LLR计算的情况下实现并行级联分组码的Turbo迭代译码。仿真研究表明,若将译码器的输出进行简单的相关运算,可进一步改善译码器性能。     

基于VHDL的TPC译码器设计

Turbo乘积码是一种性能卓越的前向纠错码,具有译码复杂度低,且在低信噪比时可以获得近似最优的性能。介绍基于Chase算法的Turbo乘积码软入软出（SISO）迭代译码算法,提出基于VHDL硬件描述语言的TPC译码器设计方案,并在FPGA芯片上进行了仿真和验证。仿真结果证明该译码器有很大的实用性和灵活性。     

基于FPGA的RS码译码器的设计

介绍了符合CCSDS标准的RS(255,223)码译码器的硬件实现结构。译码器采用8位并行时域译码算法,主要包括了修正后的无逆BM迭代译码算法,钱搜索算法和Forney算法。采用了三级流水线结构实现,减小了译码器的时延,提高了译码的速率,使用了VHDL语言完成译码器的设计与实现。测试表明,该译码器性能优良,适用于高速通信。     

基于SSCANL译码器的联合迭代检测译码算法

为了提升基于极化码的稀疏码多址接入（sparse code multiple access,SCMA）系统接收机性能,提出了基于简化软消除列表（simplify soft cancellation list,SSCANL）译码器的循环冗余校验（cyclic redundancy check,CRC）辅助联合迭代检测译码接收机方案。该方案中极化码译码器使用SSCANL译码算法,采用译码节点删除技术对软消除列表（soft cancellation list,SCANL）算法所需要的L次软消除译码（soft cancellation, SCAN）进行简化,通过近似删除冻结位节点,简化节点间软信息更新计算过程,从而降低译码算法的计算复杂度。仿真结果表明,SSCANL算法可获得与SCANL算法一致的性能,其计算复杂度与SCANL算法相比有所降低,码率越低,算法复杂度降低效果越好;且基于SSCANL译码器的CRC 辅助联合迭代检测译码接收机方案相较基于SCAN译码器的联合迭代检测译码（joint iterative detection and decoding based on SCAN decoder, JIDD-SCAN）方案、基于SCAN译码器的CRC辅助联合迭代检测译码（CRC aided joint iterative detection and decoding based on SCAN decoder,C-JIDD-SCAN）方案,在误码率为10^-4时,性能分别提升了约0.65 dB、0.59 dB。     

Turbo码高速译码器设计

Turbo码具有优良的纠错性能,被认为是最接近香农限的纠错码之一,并被多个通信行业标准所采用。Turbo码译码算法相比于编码算法要复杂得多,同时其采用迭代译码方式,以上2个原因使得Turbo码译码器硬件实现复杂,而且译码速度非常有限。从Turbo码高速译码器硬件实现出发,介绍Turbo码迭代译码的硬件快速实现算法以及流水线译码方式,并介绍利用Altera的Flex10k10E芯片实现该高速译码器硬件架构。测试和仿真结果表明,该高速译码器具有较高的译码速度和良好的译码性能。     

多元LDPC码串行译码算法在光纤通信中的应用

将串行BP译码算法用在多元LDPC码中,降低了在光纤传输系统中的译码延时.详细介绍了在多元LDPC码中的串行BP译码算法和光纤通信系统的仿真模型.给出了在采用串行BP算法的LDPC译码器中,译码最大迭代数量对译码性能的影响,比较了采用传统的BP算法扣串行BP算法时LDPC译码器的性能.结果表明,采用串行BP算法确实能够提升LDPC译码器的收敛速度.     

IEEE802.16e标准LDPC译码器设计与实现

LDPC码自在上个世纪90年代被重新发现以来,以其接近香农极限的差错控制性能,以及译码复杂度低、吞吐率高的优点引起了人们的关注,成为继Turbo码之后信道编码界的又一研究热点。利用FPGA设计并实现了一种基于IEEE802.16e标准的LDPC码译码器。该译码器采用偏移最小和（Offset Min-Sum）算法,其偏移因子β取值为0.125,具有接近置信传播（Belief Propagation）算法浮点的性能。译码器在结构上采用了部分并行结构,可以灵活支持标准中定义的所有码率和码长的LDPC码的译码。此外,该译码器还支持对连续输入的数据块进行处理,并具有动态停止迭代功能。硬件综合结果表明,该译码器工作频率为150MHz时,固定15次迭代,最低可达到95Mb/s的译码吞吐率,完全满足802.16e标准的要求。     

A parallel MAP algorithm for low latency turbo decoding

To reduce the computational decoding delay of turbo codes, we propose a parallel algorithm for maximum a posteriori (MAP) decoders. We divide a whole noisy codeword into sub-blocks and use multiple processors to perform sub-block MAP decoding in parallel. Unlike the previously proposed approach with sub-block overlapping, we utilize the forward and backward variables computed in the previous iteration to provide boundary distributions for each sub-block MAP decoder. Our scheme depicts asymptotically optimal performance in the sense that the BER is the same as that of the regular turbo decoder     

Gear-Shift Decoding

This paper considers a class of iterative message-passing decoders for low-density parity-check codes in which the decoder can choose its decoding rule from a set of decoding algorithms at each iteration. Each available decoding algorithm may have different per-iteration computation time and performance. With an appropriate choice of algorithm at each iteration, overall decoding latency can be reduced significantly, compared with standard decoding methods. Such a decoder is called a gear-shift decoder because it changes its decoding rule (shifts gears) in order to guarantee both convergence and maximum decoding speed (minimum decoding latency). Using extrinsic information transfer charts, the problem of finding the optimum (minimum decoding latency) gear-shift decoder is formulated as a computationally tractable dynamic program. The optimum gear-shift decoder is proved to have a decoding threshold equal to or better than the best decoding threshold among those of the available algorithms. In addition to speeding up software decoder implementations, gear-shift decoding can be applied to optimize a pipelined hardware decoder, minimizing hardware cost for a given decoder throughput.     

高速Reed-Solomon解码器及其FPGA的实现

提出了一种高速流水线型Reed-Solomon(RS)解码器,该解码器在Berlekamp-Massey(BM)原理基础上加以改进后更适宜用硬件描述语言(HDL)来描述并用FPGA来实现,时序仿真表明该解码器的最高时钟频率可达30MHz。对RS解码器的总体结构作了概述,并对校正子、乘法电路及改进的BM迭代作了较为详细的叙述。最后简单介绍了Xilinx的FPGA芯片的基本结构。     

Turbo decoder

We propose an adaptive channel SNR estimation algorithm required for the iterative MAP decoding of turbo decoders. The proposed algorithm uses the extrinsic values generated within the iterative MAP decoder to update the channel SNR estimate toward its optimum value per each decoder iteration or per each turbo code frame     

An efficient Chase decoder for turbo product codes

In this letter, we propose an efficient decoding algorithm for turbo product codes as introduced by Pyndiah. The proposed decoder has no performance degradation and reduces the complexity of the original decoder by an order of magnitude. We concentrate on extended Bose-Chaudhuri-Hocquengem codes as the constituent row and column codes because of their already low implementation complexity. For these component codes, we observe that the weight and reliability factors can be fixed, and that there is no need for normalization. Furthermore, as opposed to previous efficient decoders, the newly proposed decoder naturally scales with a test-pattern parameter p that can change as a function of iteration number, i.e., the efficient Chase algorithm presented here uses conventionally ordered test patterns, and the syndromes, even parities, and extrinsic metrics are obtained with a minimum number of operations.     

Reduced-Complexity Turbo Equalization for Turbo Coded MIMO/OFDM Systems

1IntroductionTowards wireless systems Beyondthe3G(B3G),it isa great challenge for the physical layer to support high-speed transmissioninthe mobile environment to providecomfortable Internet access.Multiple Input MultipleOutput(MI MO)technique is effectiv…     

Iterative Equalization using Improved Block DFE for Synchronous CDMA Systems

Iterative equalization using optimal multiuser detector and optimal channel decoder in coded CDMA systems improves the bit error rate (BER) performance tremendously. However, given large number of users employed in the system over multipath channels causing significant multiple-access interference (MAI) and intersymbol interference (ISI), the optimal multiuser detector is thus prohibitively complex. Therefore, the sub-optimal detectors such as low-complexity linear and non-linear equalizers have to be considered. In this paper, a novel low-complexity block decision feedback equalizer (DFE) is proposed for the synchronous CDMA system. Based on the conventional block DFE, the new method is developed by computing the reliable extrinsic log-likelihood ratio (LLR) using two consecutive received samples rather than one received sample in the literature. At each iteration, the estimated symbols by the equalizer is then saved as a priori information for next iteration. Simulation results demonstrate that the proposed low-complexity block DFE algorithm offers good performance gain over the conventional block DFE.     

基于FPGA的RS译码器的设计与实现

针对Reed-Solomon（RS）码译码过程复杂、译码速度慢和专用译码器价格高等问题,以联合信息分发系统终端J系列报文信息位采用的RS（31,15）码为例,介绍了基于改进的无求逆运算的Berlekamp-Massey（BM）迭代算法的RS译码原理,采用Verilog硬件描述语言对译码器中各个子模块进行了设计,并基于现场可编程门阵列平台,在QuartusII6.0环境下进行了仿真,验证了RS译码器的纠错能力,实现了参数化与模块化的RS译码器设计。     

基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.