不同温度退火的HfTiON栅介质MOS电容电特性研究

在N2/O2气氛中,使用Ti、Hf靶共反应溅射在衬底Si上淀积一种新型栅介质材料HfTiON,随后分别在N2气氛中600°C和800°C退火2min。电容电压(C-V)特性和栅极漏电流特性测试结果表明,800°C快速热退火(RTA)样品表现出更低的界面态密度、更低的氧化物电荷密度和更好的器件可靠性,这是由于在800°C下的RTA能有效地消除溅射生长过程中导致的损伤,形成高质量、高可靠性的介质/Si界面。     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

高k HfO2栅介质淀积后退火工艺研究

研究了淀积后退火(PDA)工艺(包括退火环境和退火温度)对高介电常数(k)HfO2栅介质MOS电容(MOSCAP)电学特性的影响.通过对比O2和N2环境中,不同退火温度下的HfO2栅介质MOSCAP的C-V曲线发现,高kHfO2栅介质在N2环境中退火时具有更大的工艺窗口.通过对HfO2栅介质MOSCAP的等效氧化层厚度(dEOT)、平带电压(Vfb)和栅极泄漏电流(Ig)等参数进一步分析发现,与O2环境相比,高kHfO2栅介质在N2环境中PDA处理时dEOT和Ig更小、Vfb相差不大,更适合纳米器件的进一步微缩.HfO2栅介质PDA处理的最佳工艺条件是在N2环境中600℃下进行.该优化条件下高kHfO2栅介质MOSCAP的dEOT=0.75 nm,Vnb=0.37 V,Ig=0.27 A/cm2,满足14或16 nm技术节点对HfO2栅介质的要求.     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

The material and electrical properties of HfO2 high-k gate dielectric are reported.In the first part,the band alignment of HfO2 and (HfO2)x(Al2O3)1-x to (100)Si substrate and their thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO2)x(Al2O3)1-x,the valence band offset,and the conduction band offset between (HfO2)x(Al2O3)1-x and the Si substrate as functions of x are obtained based on the XPS results.Our XPS results also demonstrate that both the thermal stability and the resistance to oxygen diffusion of HfO2 are improved by adding Al to form Hf aluminates.In the second part,a thermally stable and high quality HfN/HfO2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage,and work function (close to Si mid-gap) of HfN/HfO2 gate stack are demonstrated even after 1000℃ post-metal annealing(PMA),which is attributed to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO2 interface.Therefore,even without surface nitridation prior to HfO2 deposition,the EOT of HfN/HfO2 gate stack has been successfully scaled down to less than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.The last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO2 gate dielectric.The excellent thermal stability of the HfN/HfO2 gate stack enables its use in high temperature CMOS processes.The replacement of HfN with other metal gate materials with work functions adequate for n- and p-MOS is facilitated by a high etch selectivity of HfN with respect to HfO2,without any degradation to the EOT,gate leakage,or TDDB characteristics of HfO2.     

非晶ErAlO高k栅介质薄膜的制备及性能研究

采用射频磁控溅射法在p型Si(100)衬底上成功制备了非晶Er2O3-Al2O3(ErAlO)栅介质复合氧化物薄膜。研究了ErAlO薄膜的结构及电学特性。XRD测量显示,ErAlO薄膜具有良好的热稳定性,样品经过900℃氧气氛退火30 min后仍保持非晶态结构。AFM照片显示,其表面粗糙度小于0.2 nm,平整度良好。ErAlO栅MOS结构在氧分压为1%时,薄膜的有效相对介电常数为9.5,外加偏压(Vg)为–1 V时样品的漏电流密度为7.5×10–3 A/cm2。非晶ErAlO薄膜是一种很有希望取代SiO2的新型高k栅介质候选材料。     

Improvement of electrical and reliability properties of tantalum pentoxide by high-density plasma (HDP) annealing in N/sub 2/O

This study aims to improve the electrical characteristics and reliability of low-pressure chemical vapor deposited (LPCVD) tantalum pentoxide (Ta/sub 2/O/sub 5/) films by a new post-deposition annealing technique using high-density plasma (HDP). Experimental results indicate that excited oxygen atoms generated by N/sub 2/O decomposition from HDP annealing can effectively reduce the carbon and hydrogen impurity concentrations and repair the oxygen vacancies in the as-deposited CVD Ta/sub 2/O/sub 5/ film, thereby resulting in a remarkable reduction of the film's leakage current. Two other post-deposition annealing conditions are compared: HDP O/sub 2/ annealing and conventional plasma O/sub 2/ annealing. The comparison reveals that HDP N/sub 2/O annealing has the lowest leakage current and superior time-dependent dielectric breakdown (TDDB) reliability.     

非故意掺杂GaN上Ti/Al/Ni/Au欧姆接触研究

基于圆形传输线模型,研究了背景载流子浓度为71016cm3的非故意掺杂GaN与Ti/Al/Ni/Au多层金属之间欧姆接触的形成。样品在N2气氛中,分别经过温度450,550,700,800,900℃的1 min快速热退火处理后发现,当退火温度高于700℃欧姆接触开始形成,随着温度升高欧姆接触电阻持续下降,在900℃时获得了最低比接触电阻6.6106O·cm2。研究表明,要获得低的欧姆接触电阻,需要Al与Ti发生充分固相反应,并穿透Ti层到达GaN表面;同时,GaN中N外扩散到金属中,在GaN表面产生N空位起施主作用,可提高界面掺杂浓度,从而有助于电子隧穿界面而形成良好欧姆接触。     

低压高温退火对Ag掺杂ZnO薄膜性质的影响

采用电子束蒸发在n-Si(100)衬底上沉积Ag掺ZnO(ZnO:Ag)薄膜,随后在200 Pa的O<,2>气氛下分别在500、600、700和800℃退火4 h.用X射线衍射(XRD)仪、荧光光谱仪以及Van der Pauw方法测量ZnO:Ag薄膜的结构和光电学性质.结果表明,ZnO:Ag薄膜为多晶结构,且随着退火...     

凹栅槽AlGaN/GaN HEMTs器件退火处理效应

研究了如何减小等离子体干法刻蚀导致的大肖特基漏电.用X射线光电能谱(XPS)分析刻蚀前后的AlGaN表面,发现刻蚀后AlGaN表面出现了N窄位,导致肖特基栅电流偏离热电子散射模型,N空位做为一种缺陷使得肖特基结的隧穿几率增大,反向漏电增大,肖特基势垒降低.介绍了一种AlGaN/GaN HEMTs器件退火处理方法,优化退火条件为400℃,Nz氛围退火10min.退火后,栅金属中的Ni与Ga原子反应从而减少N空穴造成的缺陷,器件肖特基反向漏电减小三个量级,正向开启电压升高,理想因子从3.07降低到了2.08.     

Al_2O_3栅介质的制备工艺及其泄漏电流输运机制

利用室温下反应磁控溅射结合炉退火的方法在P Si(10 0 )衬底上制备了Al2 O3 栅介质层,研究了不同的溅射气氛和退火条件对Al2 O3 栅介质层物理特性的影响.结果表明:在较高温度下N2 气氛中退火有助于减小泄漏电流;在O2 气氛中退火有助于减少Al2 O3 栅介质中的氧空位缺陷.对Al2 O3 栅介质泄漏电流输运机制的分析表明,在电子由衬底注入的情况下,泄漏电流主要由Schottky发射机制引起,而在电子由栅注入的情况下,泄漏电流可能由Schot tky发射和Frenkel Poole发射两种机制共同引起.     

退火处理对锑化铟MIS器件C-V特性的影响

采用原子层沉积技术制备Al2O3薄膜作为InSb材料介电层,制备了MIS器件,研究了金属化后不同退火温度对界面特性的影响.利用C-V测试表征了MIS(metal-insulator-semiconductor)器件的界面特性,结果表明Al2O3介电层引入了表面固定正电荷,200℃和300℃退火处理可有效减小慢界面态密度...     

GaN紫外探测器的Ti/Al接触的电学特性

在非故意掺杂的和掺Si的GaN薄膜上蒸镀Ti(24nm)/Al(nm)薄膜,氮气环境下400～800℃范围内进行退火。实验结果表明,在非故意掺杂的样品上,随退火温度的升高,肖特基势垒高度下降,理想因子升高,表面状况逐渐变差,600℃退火形成较低接触电阻的欧姆接触,比接触电阻率为3.03×10-4Ωcm2,而载流子浓度为5.88×1018cm-3的掺Si的样品未退火就形成欧姆接触,比接触电阻可达到4.03×10-4Ωcm2。     

PLD法制备ZnO薄膜的退火特性和蓝光机制研究

通过脉冲激光沉积(PLD)方法,在O2中和100～500℃衬底温度下,用粉末靶在Si(111)衬底上制备了ZnO薄膜,在300℃温度下生长的薄膜在400～800℃温度和N2氛围中进行了退火处理,用X射线衍射(XRD)谱、原子力显微镜(AFM)和光致发光(PL)谱表征薄膜的结构和光学特性。XRD谱显示,在生长温度300℃时获得较好的复晶薄膜,在退火温度700℃时获得最好的六方结构的结晶薄膜;AFM显示,在此退火条件下,薄膜表面平整、晶粒均匀;PL谱结果显示,在700℃退火时有最好的光学特性。     

On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

The work function of ALD TiN was found to be above 5 eV after RTP annealing below 800/spl deg/C in a nitrogen atmosphere, while higher annealing temperatures cause a drop in work function by about 0.3-0.5 eV. The effect was found for TiN metal gates on both SiO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics in MOS-capacitors and was seen in C-V as well as in I-V measurements. On the contrary, annealing of SiO/sub 2/ capacitors in oxygen-enriched N/sub 2/ atmosphere increased the work function. A variation in EOT of less than 2 A was demonstrated for the various annealing temperatures, concluding that the ALD TiN is stable in contact with the different dielectric materials. However, the decrease in work function that is found in this investigation may implicate that ALD TiN is less suitable as a metal gate for pMOSFETs.     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

Introduction High- k gate dielectrics have been extensivelystudied as alternates to conventional gate oxide( Si O2 ) due to the aggressive downscaling of Si O2thickness in CMOS devices,and hence the exces-sive gate leakage.Hf O2 has emerged as one...     

硅衬底注氮方法制备超薄SiO2栅介质

利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N+注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.     

不同气体退火La_2O_3栅介质Ge MOS电容的电特性

采用电子束蒸发方法,在Ge衬底上淀积La_2O_3高k栅介质,研究了O_2、NO、NH_3和N_2不同气体退火对MOS电容电特性的影响。测量了器件的C-V和I-V特性,并进行了高场应力实验。结果表明La_2O_3在N_2气氛中退火后,由于形成稳定的LaGeO_x而有效地降低了Q_(ox)和D_(it),从而获得低的栅极漏电流,同时获得较高的栅介质介电常数(18)。     

Pt层对Ni/Si(100)固相反应NiSi薄膜高温稳定性的增强效应

研究了顺次淀积在Si(100)衬底上的Ni/Pt和Pt/Ni的固相硅化反应．研究发现,当1nm Pt作为中间层或覆盖层加入Ni/Si体系中时,延缓了NiSi向NiSi2的转变,相变温度提高．对于这种双层薄膜体系,800℃退火后,XRD测试未检测到NiSi2相存在;850℃退火后的薄膜仍有一些NiSi衍射峰存在．800℃退火后的薄膜呈现较低的电阻率,在23—25μΩ*cm范围．上述薄膜较Ni/Si直接反应生成膜的热稳定性提高了100℃以上．这有利于NiSi薄膜材料在Si基器件制造中的应用．     

Effects of post-deposition annealing on the electrical propertiesand reliability of ultrathin chemical vapor deposited Ta2O5 films

This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta₂O₅ (~10 nm) on NH₃-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800°C rapid thermal O₂ annealing (RTO) for 20 sec followed by rapid thermal N₂ annealing (RTA) for 40 sec, b) 800°C RTO for 60 sec and c) 900°C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta₂O₅/poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics     

预烧温度对PZN-PZT压电陶瓷电性能的影响

采用传统固相法制备了化学计量比为0.3Pb(Zn1/3Nb2/3)O3-0.35PbTiO3-0.35PbZrO3的压电陶瓷,研究了所制陶瓷的预合成温度对其微观结构和压电介电性能的影响。结果显示,当预合成温度大于800℃时可以获得纯钙钛矿相,低于800℃钙钛矿主晶相不明显且有很多杂相产生。当预烧温度为775℃时,经1 125℃保温3 h烧结的陶瓷具有最佳综合性能:d33=431 pC/N、k31=0.36、Ec=9.98×103 V/mm、Pr=22.52×10–6 C/cm2、εr=1 874、tanδ=0.024、ρ=7.88 g/cm3。