Operation Principles of 0.18-$muhboxm$Four-Transistor CMOS Image Pixels With a Nonfully Depleted Pinned Photodiode

The operation principles of the four-transistor (4-TR) pixel CMOS image sensor, fabricated by 0.18-mum technology, were investigated by pixel-level characterization utilizing a single-pixel test pattern. It was found that the pixel's dark current level is strongly influenced by the gate bias (V_TX(on)) of the transfer (TX) transistor at a fixed supply voltage (V_DD). The largest dark current occurred at a conventional bias condition of V_TX(on)=V_DD=2.5V, but the dark current level was reduced by less than one-third at V_TX(on)=2.1V without degrading the pixel's charge transfer capabilities. Attributed to the dark current reduction, the fixed-pattern noise (FPN) of pixel was also decreased by up to 13.3 dB. These improvements can be explained by the more effective reset of pinned photodiode (PPD) at V_TX(on)=2.1V, especially in the pixel with V_DD of 2.5 V or lower in which the full depletion of PPD becomes more and more difficult. In this bias condition, namely nonfully depletion PPD condition, the TX transistor was proven to operate in the "deepest depletion" mode by effectively suppressing the electron injection from floating diffusion node to channel. Moreover, various driving signals to the TX transistor were applied to do more detailed physical analysis of the pixel operation. Since the dark current and FPN are main bottlenecks in most CMOS image sensors, the proposed method is expected to efficiently improve the performance of 4-TR CMOS image pixels under 2.5 V or lower operational voltages     

新型电流镜积分红外量子阱探测器读出电路的设计分析

设计了一种偏压可调电流镜积分(Current Mirroring Integration,CMI)红外量子阱探测器焦平面CMOS读出电路。该电路适应根据偏压调节响应波段的量子阱探测器,其中探测器偏压从0.61 V到1.55V范围内可调。由于CMI的电流反馈结构,使得输入阻抗接近0,注入效率达0.99;且积分电容可放在单元电路外,从而可以在一定的单元面积下,增大积分电容,提高了电荷处理能力和动态范围;为提高读出电路的性能,电路加入撇除(Skimming)方式的暗电流抑制电路。采用特许半导体(Chartered)0.35 m标准CMOS工艺对所设计的电路(16×1阵列)进行流片,测试结果表明:在电源电压为3.3V,积分电容为1.25pF时,电荷处理能力达到1.3×107个电子;输出摆幅达到1.76V;功耗为25mW;动态范围为75dB;测试结果显示CMI可应用于高性能FPA。     

Low-power single-to-differential LNA at S-band based on optimised transformer topology and integrated ESD

A single-ended to differential low-power low-noise amplifier (LNA) designed and implemented in 0.18 mum CMOS technology is presented. The device takes advantage of a current reuse strategy by stacking two common-source differential transistor pair stages for minimum current dissipation, together with the design of optimised high Q differential transformers and inductors in order to minimise the impact of parasitics. The fully integrated, including ESD protection diodes, 2.1 GHz LNA consumes 1.1 mW at 1.2 V supply voltage and presents 29.8 dB gain, 4.5 dB noise figure, -21.1 dBm 1 dB compression point, -11.6 dBm input third-order intercept point and -12.3 dB input return loss performance.     

Transversal-readout architecture for CMOS active pixel image sensors

Novel architecture for CMOS active pixel image sensors (APSs), which eliminates the vertically striped fixed pattern noise (FPN), is presented. There are two kinds of FPN for CMOS APSs. One originates from the pixel-to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which results in a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and column-reset transistor, a source-follower input transistor, and a column-select transistor instead of the row-select transistor found in conventional CMOS APSs. The column-select transistor is connected to a signal line that runs horizontally instead of vertically. An experimentally fabricated 320/spl times/240-pixel CMOS APS employing the transversal-readout architecture exhibited neither vertically nor horizontally striped FPN. A buried-photodiode device with the transversal-readout architecture is also proposed.     

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.     

一种基于动态阈值NMOS的1.2 V CMOS模拟乘法器

分析了以动态阈值NMOS晶体管作为输入信号的输入晶体管,利用4个动态阈值NMOS和2个有源电阻设计和实现的一种1.2 V低功耗CMOS模拟乘法器电路。该电路具有节省输入晶体管数目、偏置晶体管和偏置电路,以及性能指标优良的特点。其主要参数指标达到:一、三次谐波差值40 dB,输出信号频带宽度375 MHz,平均电源电流约30 μA,动态功耗约36 μW。可直接应用于低功耗通信集成电路设计。     

一种面向单片DC/DC的低压高效片上电流检测技术

本文提出并实现了一种面向电流模式单片开关DC/DC转换器的低压高效片上电流采样电路.该电路利用功率管等效电阻电流检测技术和无需OP放大器的源极输入差分电压放大技术,使电路的应用范围可低达2.3V;-3dB带宽12MHz;在最大负载电流情况下的静态电流峰值仅19μA,比常规采用功率管镜像电流检测技术的静态电流峰值低1.5个量级左右.转换器基于0.5μm 2P3M Mixed Signal CMOS工艺设计制作.测试结果表明,电流检测电路的最大检测电流1.1A,转换器的输入最低电压2.3V,重负载转换效率高于93%.     

A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-/spl mu/m-long 1.2-V thin-oxide transistor with a 0.22-/spl mu/m-long 3.3-V thick-oxide transistor in a 0.13-/spl mu/m CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 /spl mu/m is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 /spl mu/m) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V/sub T/) and breakdown voltage in conventional CMOS technologies without adding any process modifications.     

一种新颖的带背景抑制红外读出单元电路

设计了一种带新型背景抑制技术的红外读出电路,该电路通过控制开关管的导通与关断,使背景抑制电流源在积分过程中间断性地产生背景抑制电流.同时,背景抑制电流产生管工作在强反型区,减小了由工艺失配和噪声所引起的单元电路间背景抑制电流的变化,降低了电路的背景抑制非均匀性.所提出的读出电路基于CSMC DPTM(双晶三铝)0.5 ...     

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

An ultra-low-voltage ultra-low-power CMOS active mixer

The scaling of CMOS technology has greatly influenced the design of analog and radio-frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption that is capable of operating from a supply voltage comparable or lower than the threshold voltage of the transistor. In addition, the proposed architecture provides a performance and conversion gain (CG) that compares favorably or exceeds those of the state-of-the-art designs. As a proof-of-concept, a wide-band DC to 8.5 GHz down-conversion mixer is designed and fabricated in a 90-nm CMOS process. Measurement results show that the mixer achieves a CG as high as 18 dB while consuming 98 μW from a 0.3-V supply.     

A novel CMOS multivibrator

The paper describes a CMOS multivibrator using a differential pair with positive feedback via a current mirror and a diode-connected NMOS transistor; the output voltage is taken at this transistor. The timing capacitor is charged by a current source and discharged by the differential pair tail current. During capacitor charging the tail current is steered into the current mirror. The mirror output current is applied to a diode-connected transistor and creates the HIGH level of the output voltage. During discharging the diode connected transistor obtains a small current (from another current source) which determines the LOW level of the output voltage. The capacitive loading and frequency limit are investigated. The design procedure is given. The body effect does not affect the circuit performance. This allows to reduce the multivibrator area.     

A Single Transistor‐Level Direct‐Conversion Mixer for Low‐Voltage Low‐Power Multi‐band Radios

A CMOS direct‐conversion mixer with a single transistor‐level topology is proposed in this paper. Since the single transistor‐level topology needs smaller supply voltage than the conventional Gilbert‐cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system‐on‐a‐chip (SoC). The proposed direct‐conversion mixer is designed for the multi‐band ultra‐wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and ?10 dBm, respectively, with multi‐band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage.     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs)

This paper reports a 21.5-dBm power-handling 5-GHz transmit/receive CMOS switch utilizing the depletion-layer-extended transistor (DET), which possesses high effective substrate resistance and enables the voltage division effect of the stacked transistor configuration to work in the CMOS switch. Furthermore, low insertion losses of 0.95 and 1.44 dB are accomplished at 5 GHz in the transmit and receive modes, respectively, with the benefit of the insertion-loss improvement effects in the DET. At the same time, high isolations of more than 22 dB were obtained at 5 GHz in the transmit and receive modes with the adoption of the shunt/series type circuit.     

A sub-mW 2.9-dB noise figure Inductor-less low noise amplifier for wireless sensor network applications

In this paper, a low power differential inductor-less Common Gate Low Noise Amplifier (CG-LNA) is presented for Wireless Sensor Network (WSN) applications. New Shunt feedback is employed with noise cancellation and Dual Capacitive Cross Coupling (DCCC) techniques to improve the performance of common gate structures in terms of gain, Noise Figure (NF) and power consumption. The shunt feedback path boosts the input conductance of the LNA in current reuse scheme. Both shunt feedback and current reuse bring power dissipation down considerably. In addition, the positive feedback is utilized to cancel the thermal noise of the input transistor. The proposed LNA is designed and simulated in 0.18 µm TSMC CMOS technology. Post layout Simulation results indicate a voltage gain of 16.5 dB with −3 dB bandwidth of 100 MHz–3 GHz. Also third order Input Intercept Point (IIP3) is equal to + 1 dBm. The minimum NF is 2.8 dB and the value of NF at 2.4 GHz is 2.9 dB. S11 is better than −13 dB in whole frequency range. The core LNA consumes 985 µW from a 1.8 V DC voltage supply.     

A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells

A 31.3-dBm 900-MHz bulk CMOS T/R switch with transmit (TX) and receive (RX) insertion losses of 0.5 and 1.0 dB and isolation of 29 dB is demonstrated. The switch utilizes a floating-body technique, feed-forward capacitors, and 3-stack 3.3-V MOSFETs with 0.26-mum sub-design-rule (SDR) channel length. Using these, a 28-dBm 2.4-GHz T/R switch with TX and RX insertion losses of 0.8 and 1.2 dB, and isolation of 24 dB is also demonstrated. The power handling capability is limited by an abrupt output power drop before reaching the normal 1-dB compression point. The circuits are implemented in the UMC 130-nm mixed-mode triple-well CMOS process.     

A charge pump for driving CMOS active pixel reset

To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.     

A dynamic photoresponse model for a pinned photodiode in CMOS image sensors

A novel dynamic photoresponse model for complementary metal-oxide-semiconductor (CMOS) image sensors with pinned photodiode (PPD) structures is proposed. The PPD is regarded as the bonding structure of the two p-n junctions. The transient current equation of the two junctions is calculated by the current-voltage formula of the p-n junction, and the photoresponse curve of the PPD is calculated and drawn by the numerical solution. Simulation results show that the dynamic model successfully restores the entire process of the electron accumulation in the PPD. The difference between the full well capacity (FWC) values which were calculated by the proposed model and the simulation results is less than 5%, which is much smaller than the error of 40% for the traditional model.     

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

A 4-Mb (512 K words by 8-b) CMOS static RAM (SRAM) with a PMOS thin-film transistor (TFT) has been developed. The RAM can obtain a much larger data-retention margin than a conventional high-resistive load-type well by using the PMOS TFT as a memory cell load. An internal voltage down-converter architecture with an external supply voltage-level sensor not only realizes a highly reliable 0.5-μm MOS transistor operation but also a sufficiently low standby-power dissipation characteristic for data battery-backup application. A self-aligned equalized level sensing scheme can minimize the sensing delay for a local sense amplifier to drive a large load capacitance of a global sensing bus line. The RAM is fabricated using a 0.5 μm, triple-poly, and double-aluminum with dual gate-oxide-thickness CMOS process technology. The RAM operates under a single 5-V supply voltage with 23-ns typical address access time and 20- and 70-mA operation current at 10 and 40 MHz, respectively