高性能半静态双边沿D触发器

在分析现有静态结构双边沿触发器和动态结构双边沿触发器优缺点的基础上，该文提出了半静态结构双边沿触发器设计。PSPICE模拟表明，新设计功能正确。与以往一些设计柏比，新设计在功耗、速度、功耗延迟秘以及减少MOS晶体管使用数目等方面都具有明显的优势，从而使新设计具有良好的综合性能。该文的另一个贡献是对双边沿触发器性能的测试方法进行了探讨，提出了测试双边沿触发器最高频率的新方法。     

三值触发器设计及其变换

本文研究了基于状态图设计三值触发器的通用方法，对称和非对称三值逻辑均适用，用一个状态图统一地导出主从结构和维持阻塞结构触发器，以及其它等效触发器。本文设计出双及性ｃｐ触发器，改进了ＲＳＲ和ＪＫ触发器。     

基于74LS112JK触发器的抢答器设计

根据JK触发器在每个时钟脉冲作用时间内，其状态只变化一次，而且不同引脚都可以使触发器状态发生改变的特性，给出了用JK触发器来设计抢答器的设计方法及仿真，同时给出了用74LS112JK触发器设计抢答器的最优设计方法及思路。     

一种新型准静态D─触发器设计

本文将介绍一种新型的ＣＭＯＳ准静态Ｄ─触发器的结构，这种新结构结合了ＮＭＯＳ结构和ＣＭＯＳ结构的优点。在这篇论文中将这种新型结构与ＮＭＯＳ传输门Ｄ─触发器、普通ＣＭＯＳ传输门Ｄ─触发器在结构、功能、集成度和特性等方面进行了比较，讨论这种新结构中ＭＯＳ管尺寸的设计，并且通过电路模拟软件ＳＰＩＣＥ对电路进行特性分析和比较。     

可预置绝热触发器的设计及其应用

研究了采用交流能源的可预置绝热触发器。首先对CMOS电路的能量恢复原理进行了分析，在此基础上，提出了性能良好的低功耗绝热触发器，并设置了它的预置控制端，使该触发器可方便地应用于时序电路设计。验征了采用该触发器设计时序系统的实例。SPICE模拟表明，所设计的电路具有正确的逻辑功能及低功耗的优点。     

双阶跃JK触发器和多阶跃时序电路

本文首先分析双阶跃ＪＫ触发器完成的功能，推出它的特征方程，并设计其电路，然后用该触发器设计多阶跃时序电路。     

多值时钟与并列式多拍多值触发器

通过对现有多值主从触发器－串列式二拍多值主从触发器的分析，本文指出了这些触发器并不符合使用信号增加信息携带量的要求，从而提出了采用多值时钟的并列式多拍多值触发器，并设计了四值Ｄ触发器，这种发器具有存贮能力强，逻辑结构丰富的特点。     

用单片机实现串级调速

利用单片机实现三相绕线式异步电动机改变转差调速系统，触发器设计为频率适应式可控硅触发器，利用锁相环电路实现频率适应功能、触发器的逻辑功能由８０３５来完成。     

SQL Server 2000触发器技术及应用

触发器是SQL Server为应用程序开发人员提供的一种保证数据库中数据完整性的方法．它是一种特殊的存储过程。介绍了SQL Server触发器的概念和类型，总结了SQL Server触发器在程序设计中的应用，并给出了SQL Server触发器应用实例。     

扫描法可测性设计中扫描触发器的最优实现

提出了扫描法可测性设计中扫描触发器的最优实现方法，采用该方法每个触发器仅需增加２个ＭＯＳ管即可构成扫描触发器，比用传统方法减少１２个ＭＯＳ管，而增加的额外管脚数与传统方法一样。这样，即使采用全扫描设计，也仅需较小的芯片面积。     

Low power flip-flop with clock gating on master and slave latches

A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity     

A novel high-speed sense-amplifier-based flip-flop

A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.     

Low power double edge-triggered flip-flop using one latch

A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit data are sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops     

A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems

In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- $mu{hbox{m}}$ technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.      

Low clock-swing conditional-precharge flip-flop for more than 30%power reduction

A low clock-swing flip-flop based on a conditional precharge scheme is proposed to save both clock system power and supply power. Unlike previous reduced clock-swing flip-flops, the new flip-flop will not precharge and discharge when the input data do not change. Compared with previous low clock-swing flip-flops, the new flip-flop leads to savings of at least 30% of the total power     

Reduced setup time static D flip-flop

The design of a reduced setup time static D type flip-flop is described. The setup time of the proposed static D flip-flop is equivalent to that of dynamic D flip-flops     

Loosely coupled multi-bit flip-flop allocation for power reduction

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this work, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space. Utilizing LC-MBFFs, we propose a multi-bit flip-flop allocation algorithm which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.51% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%. Additionally, we extend our algorithm to support the multi-bit flip-flop allocation for circuits with clock polarity assignment.     

Level conversion for dual-supply systems

Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Additionally, circuit robustness against supply bounce is a key property that differentiates good level converter design. Novel flip-flops presented in this paper incorporate a half-latch level converter and a precharged level converter. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip-flop. These benefits are accompanied by 24% flip-flop robustness improvement leading to 13% delay spread reduction in a CVS critical path. The proposed flip-flops also show 18% layout area reduction. Advantages of level conversion in a flip-flop over asynchronous level conversion in combinational logic are also discussed in terms of delay penalty and its sensitivity to supply bounce.     

采用三相交流电源的低功耗绝热时序电路

研究采用三相交流电源的绝热时序电路.首先介绍了采用三相交流电源的双传输门绝热电路并分析其工作原理，在此基础上提出了性能良好的低功耗绝热D、T与JK触发器.使用绝热触发器设计时序系统的实例被演示.SPICE程序模拟表明，设计的电路具有正确的逻辑功能及低功耗的优点。     

能量回收技术在D触发器上的应用

将能量回收技术应用于灵敏放大器型D触发器(SAERD),该电路采用单相正弦时钟,用来回收时钟端的能量,对于触发器的内部节点和存储单元仍采用恒定电源。在时钟频率为100～300MHz时,时钟端的功耗较输入方波时平均节省约80%。在SMIC0.13μm工艺下将SAERD应用于一款函数发生器,并与传统主从型D触发器(MSD)实现的电路进行功耗比较。仿真结果显示,时钟频率为200MHz时,功耗节省高达17.1%。