共查询到20条相似文献,搜索用时 125 毫秒
1.
2.
基于小波变换的非均匀采样信号频谱的研究 总被引:7,自引:0,他引:7
该文提出基于小波变换的非均匀采样信号频谱的检测方法,给出变换函数关系使得非均匀采样信号满足小波变换的两个基本条件。文中说明了小波的非均匀化过程,从均匀小波得到非均匀小波,以非均匀小波分析非均匀采样信号,得到非均匀采样信号的频谱。文中还说明了非均匀小波变换的抗混叠的原理以及对信号频谱的检测方法,最后给出实验结果。理论和实验表明,非均匀采样信号的小波变换方法是一种行之有效的非均匀采样信号的频率检测方法,使用该方法处理信号可以得到准确的频率估计效果。 相似文献
3.
一种非均匀采样下小信号的检测方法 总被引:2,自引:0,他引:2
非均匀采样由于其具有不受采样频率限制、频率分辨率高以及抗混叠等优点,使得其应用十分广泛。但非均匀采样会引起信号的频谱噪声,这样使得非均匀采样下小信号的检测不易实现。本文分析了非均匀采样引起频谱噪声的原因,提出一种基于非均匀采样的小信号检测方法。该方法根据非均匀采样检测得到的大幅度信号,应用陷波器将其消除,降低了由大信号引起的频谱噪声,从而检测出小信号。文中详细说明了陷波方法的原理、陷波器宽度和深度的选择、陷波器中心频率的确定以及陷波器在非均匀采样下的应用,最后给出实验结果。理论和实验表明,基于非均匀采样的陷波方法是一种行之有效的信号频率检测方法,使用该方法处理信号可以得到准确的频率估计效果,检测出信号幅度相差100倍以上的多个信号频率。 相似文献
4.
欠采样环境下信号多频率估计 总被引:11,自引:0,他引:11
在信号欠采样环境下,本文基于时延技术和MUSIC算法提出了一种新的信号多频率估计方法,只要合适地选取时延器的延迟时间,频率估计是无模糊的。计算机模拟实验表明此方法是可行的。 相似文献
5.
讨论了非均匀采样信号简化分数阶傅立叶变换(RFRFT)域频谱重构的方法,推导了利用原信号的连续频谱无偏估计重构信号的算法,并得到了重构公式,验证了RFRFT域非均匀采样信号重构的可实现性.同时仿真了RFRFT域上非均匀采样信号的重构实施例,验证了该方法在RFRFT域上非均匀采样信号重构的准确性和稳定性. 相似文献
6.
在信号欠采样下,本文基于时延技术和四阶累积量提出一种新的信号频率直接估计方法。只要合适地选择延迟器的时延,信号频率估计无模糊。同时,方法适用于任意高斯噪声环境。计算机模拟实验表明方法是可行的。 相似文献
7.
非均匀子波空间采样定理 总被引:4,自引:0,他引:4
本文从非均匀采样出发,详细研究了非均匀采样的Walter子波空间采样定理的存在条件,给出了Shannon采样定理的一类非均匀采样形式,对紧支尺度函数张成的子波空间,给出了一类非均匀采样方法,使得对该空间中任意紧支信号,非均匀采样成为可能,文中还指出了非均匀紧支子汉空间采样的优点,数值实例验证了理论的正确性。 相似文献
8.
9.
基于伪非均匀采样的高精度时间间隔测量方法 总被引:3,自引:2,他引:1
为提高脉冲激光测距的精度,采用一种新的高精度时间间隔测量方法。在脉冲计数法的基础上,利用温补晶振生成与计时量化时钟同步同频率的参考正弦波信号,将提高时间间隔测量精度问题转化为初始相位估计;通过伪非均匀采样方法对参考正弦波信号采样,并针对研究中所采用的伪非均匀采样方法推导出相应的理论公式,然后利用最小二乘法对采样数据进行曲线拟合,将伪非均匀采样信号还原成被采样的参考信号,实现相位估计,从而实现高精度时间间隔测量。将本文方法应用于脉冲激光测距仪中,实验表明,测距仪的测距精度优于±5mm。 相似文献
10.
欠采样环境下信号多频率估计 总被引:2,自引:0,他引:2
在信号欠采样环境下,本文基于时延技术和MUSIC算法提出了一种新的信号多频率估计方法.只要合适地选取时延器的延迟时间,频率估计是无模糊的.计算机模拟实验表明此方法是可行的. 相似文献
11.
文章介绍了一款基于华润上华的0.5μm DPTM CMOS工艺的∑-Δ ADC设计方法和实现过程。同时对∑-ΔADC实现的基本原理、过采样技术和噪声整形技术进行了论述。最后对其在具体的电路中的实现方法作了相应的探讨。 相似文献
12.
Elbornsson J. Gustafsson F. Eklund J.-E. 《Signal Processing, IEEE Transactions on》2005,53(4):1413-1424
To significantly increase the sampling rate of an analog-to-digital converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the time mismatch errors. The estimation method requires no knowledge about the input signal, except that it should be band limited to the foldover frequency /spl pi//T/sub s/ for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the time errors. The Cramer-Rao bound (CRB) for the time error estimates is also calculated and compared to Monte Carlo simulations. The estimation method has also been validated on measurements from a real time-interleaved ADC system with 16 ADCs. 相似文献
13.
Elbornsson J. Gustafsson F. Eklund J.-E. 《IEEE transactions on circuits and systems. I, Regular papers》2004,51(1):151-158
To significantly increase the sampling rate of an A/D converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system. 相似文献
14.
15.
A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB. 相似文献
16.
樀要:该文描述了一种常用的多通道ADC板设计,探讨了作为多通道ADC板设计时难点之一的同步采集技术,为多通道ADC板的设计提供了一种简单有效的方法。 相似文献
17.
OFDM系统中基于信号分布函数的AGC算法 总被引:1,自引:0,他引:1
在正交频分复用系统中,传统自动增益控制(Automatic Gain Control,AGC)估计接收功率的误差很大。该文提出OFDM系统中基于信号分布函数的AGC算法,该算法通过统计模数变换器(Analog to Digital Converter,ADC)输出信号的分布函数来估计接收功率,克服了ADC截断效应的影响。仿真结果表明,在OFDM系统中,该文给出的AGC算法在一次估计后,估计误差小于0.23dB,而传统AGC算法的估计误差小于9dB。因此该文的AGC算法能更精确地估计接收功率,并能大幅度提高系统性能。 相似文献
18.
Anush Bekal Saloni Varshney Kamal Prakash Pandey 《International Journal of Electronics》2013,100(9):1427-1446
This paper presents the design, fabrication and tested results of an analogue-to-digital converter (ADC) using linear relationship ratio of comparator and resolution. An original N-bit flash architecture uses 2N?1 comparators (N = resolution), while the proposed architecture uses only N comparators for N-bit making it a linear relationship design. This paper also deals with the design of sample and hold circuit that utilises clock bootstrapping technique which allows sampling at peak voltages and helps in minimising charge injection errors, attaining 125 µV for the proposed design. The proof of concept of 4-bit prototype ADC using 1P?2M is fabricated using AMIS 500 nm CMOS C5X technology and the experimental results at a sampling rate of 800 MS/s reveal an effective no. of bit of 3.34 bits, signal-to-noise ratio of 24.44 dB and differential non-linearity and integral non-linearity of 0.42 and 0.40, respectively. The converter consumes 7 mW power when operated on 2.5 V supply and occupies 0.014 mm2 chip area. 相似文献
19.