VLSI容错设计研究进展(1)——缺陷的分布模型及容错设计的关键技术

随着芯片面积的增加及电路复杂性的增强，芯片的成品率逐渐下降，为了保证合理的成品率，人们将容错技术结合入了集成电路。文中首先概述了缺陷及其分布，然后概述了容错技术，并详细地叙述了动态容错技术中的两个关键问题：故障诊断及冗余单元的分配问题。     

VLSI容错设计研究进展（1）——缺陷的分布模型及容错设计的？…

随着芯片面积的增加及电路复杂性的增强,芯片的成品率逐渐下降,为了保证合理的成品率,人们将容错技术结合入了集成电路。文中首先概述了缺陷及其分布,然后概述了容错技术,并详细地叙述了动态容错技术中的两个关键问题：故障诊断及冗余单元的分配问题。     

各种规模集成电路

9915120步进电机微机控制卡的研制[刊]/陆渭林//声学与电子工程.—1999,(2).—34～39(D)9915121VLSI 容错设计研究进展(1):缺陷的分布模型及容错设计的关键技术[刊]/郝跃//固体电子学研究与进展.—1999,19(1).—20～32(D)随着芯片面积的增加及电路复杂性的增强,芯片的成品率逐渐下降.为了保证合理的成品率,人们将容错技术结合人了集成电路。文中首先概述了缺陷及其分布,然后概述了容错技术,并详细地叙述了动态容错技术中的两个关键问题:故障诊断及冗余单元的分配问题。参37     

实时信号处理用VLSI的容错设计

随着微电子技术的发展,集成电路的芯片面积、集成度愈来愈大。芯片面积及集成度的增大带来了两个问题:一是成品率问题,二是可靠性问题。本文阐述了容错设计在实时信号处理用VLSI中的必要性、意义和研究内容;讨论了二维脉动阵列的容错并给出了算法;讨论了VLSI单元的完全自检查问题,并给出了实现电路;给出了VLSI的成品率与可靠性分析模型;最后分析了模拟结果并给出了结论。     

混合搜索策略及其在VLSI冗余最优分配中的应用

容错技术对于提高VLSI电路的可靠性和成品率十分重要。为实现容错，系统必须提供冗余。本文利用模拟退火、禁忌搜索等现代优化算法求解VLSI系统中基于全局冗余的最优分配问题，并在此基础上提出结合两者优势的混合搜索策略TS^2A。实验结果表明，该方法在搜索质量上优于单一的优化方法。     

微电子文摘

1 IC CAD/CAT/CAM技术WD93101 适用于容错单片集成电路的成品率统计模型=在设计容错结构超大规模集成电路时,为了选取最佳冗余形式,必须评估采用各种冗余方法的电路成品率。本文介绍了适用于具有冗余结构的VLSI的成品率统计模型。根据文中描述的模型,有一个广义的负二项式分布,而且这种分布取决于利用玻色-爱因斯坦统计学或麦克斯韦-玻耳兹曼统计学的碎屑缺陷尺寸。文章推导出了适合表征电路模型间的缺陷正规和非正规分布时不同冗余方法的电路成品率表达式。参7(下一)     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

SRAM的高成品率优化设计技术

提出了一种嵌入式SRAM的高成品率优化方法:通过增加冗余逻辑和电熔丝盒来代替SRAM中的错误单元。利用二项分布计算最大概率缺陷字数,从而求出最佳冗余逻辑。将优化的SR SRAM64 K×32应用到SoC中,并对SR SRAM64K×32的测试方法进行了讨论。该SoC经90 nm CMOS工艺成功流片,芯片面积为5.6 mm×5.6 mm,功耗为1997 mW。测试结果表明:优化的SR SRAM64 K×32在每个晶圆上的成品数增加了191个,其成品率提高了13.255%。     

二分图的无关分解及其在覆盖问题中的应用

为了大容量存贮器制造过程中因缺陷而造成成品率低的问题，或并行阵列中的容错重组问题，一般采用冗余修复的方法，该问题可以归结为对二分图的覆盖，且该问题属于ＮＰ完全问题。     

民用机载电子硬件的SEU效应FPGA仿真测试研究

针对民用机载电子硬件的现场可编程门阵列(FPGA)芯片高使用频率和长时间运行的特点,以及联邦航空管理局(FAA)等提出的审查条例对单粒子翻转效应(SEU)的防护要求,介绍了民用机载电子硬件的SEU效应评估研究的必要性。并且从民用机载电子硬件主流的三模冗余容错电路入手,设计了SEU效应仿真测试电路。将冗余系统与多时钟沿触发相结合,提高了系统的检错能力。对冗余系统进行仿真SEU故障注入,通过与参照单元的比较,可对SEU效应引起的失效的发生进行仿真测试。     

Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system’s reliability.     

Fault tolerant system based on IDDQ testing

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.     

Accurate Conjunction of Yield Models for Fault-Tolerant Memory Integrated Circuits

Critical defects, i.e., faults, inevitably occur during semiconductor fabrication, and they significantly reduce both manufacturing yield and product reliability. To decrease the effects of the defects, several fault-tolerance methods, such as the redundancy technique and the error correcting code (ECC), have been successfully applied to memory integrated circuits. In the semiconductor business, accurate estimation of yield and reliability is very important for determining the chip architecture as well as the production plan. However, a simple conjunction of previous fault-tolerant yield models tends to underestimate the manufacturing yield if several fault-tolerance techniques are employed simultaneously. This paper concentrates on developing and verifying an accurate yield model which can be applied successfully in such situations. The proposed conjunction model has been derived from the probability of remaining redundancies and the average number of defects after repairing the defects with the remaining redundancies. The validity of the conjunction yield model is verified by a Monte Carlo simulation.      

Fault-tolerant evolvable hardware using field-programmabletransistor arrays

The paper presents an evolutionary approach to the design of fault-tolerant VLSI (very large scale integrated) circuits using EHW (evolvable hardware). The EHW research area comprises a set of applications where GA (genetic algorithms) are used for the automatic synthesis and adaptation of electronic circuits. EHW is particularly suitable for applications requiring changes in task requirements and in the environment or faults, through its ability to reconfigure the hardware structure dynamically and autonomously. This capacity for adaptation is achieved via the use of GA search techniques, in our experiments, a fine-grained CMOS (complementary metal-oxide silicon) FPTA (field-programmable FPGA transistor array) architecture is used to synthesize electronic circuits. The FPTA is a reconfigurable architecture, programmable at the transistor level and specifically designed for EHW applications. The paper demonstrates the power of EA to design analog and digital fault-tolerant circuits. It compares two methods to achieve fault-tolerant design, one based on fitness definition and the other based on population. The fitness approach defines, explicitly, the faults that the component can encounter during its life, and evaluates the average behavior of the individuals. The population approach, on the other hand, uses the implicit information of the population statistics accumulated by the GA over many generations. The paper presents experiment results obtained using both approaches for the synthesis of a fault-tolerant digital circuit (XNOR) and a fault-tolerant analog circuit (multiplier)     

Design of a self-reconfiguring interconnection network forfault-tolerant VLSI processor arrays

An interconnection network capable of spontaneously reconfiguring a VLSI processor array on detection of faulty processors is presented. Although the reconfiguration process is global, the network control circuitry is localized around each processor and is therefore completely modular. The structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors. The network performance in yield enhancement is analyzed through Monte Carlo simulation. The network effectiveness in using surviving processors is close to that of an ideal network (one capable of tolerating as many faulty processors per row as there are spare processors per row). Strategies involved in testing the fault-tolerant array are also presented. Test circuitry is placed around each of the processors to enable testing of all the processors in parallel. The same circuitry is used to test the interconnection network efficiently. The additional silicon area requirements due to the network and the test circuitries are examined through the design of a prototype fault-tolerant array     

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy

The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.

     

集成电路合格率优化方法的研究

本文引入了一个概率空间来描述集成电路合格率优化问题，并将合格率表示为可行域的概率测度。所提出的变权重ＭｏｎｔｅＣａｒｌｏ法适合于合格率不太高的场合，而改进后的ＳＡ算法则适合于合格率比较高的场合。这些方法已应用于ＹＯＳＩＣ系统中，并取得了满意的效果。     

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs

As one of the main trends of communication technology for 3D integrated circuits, the 3D networks-on-chip (NoCs) have drawn high concern from the academia. The links are main components of the NoCs. For the permanent link faults, the fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of the 2D NoCs. In this paper, we propose a low-overhead fault-tolerant routing scheme called LOFT for 3D Mesh NoCs without requiring any virtual channels (VCs). LOFT is a deadlock-free scheme by adopting a logic-based routing named LBDRe² guided by a turn model Complete-OE. The experimental results show that LOFT possesses better performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing schemes.