New Soft Output Viterbi Algorithm for Mobile Communication System

Soft output Viterbi algorithm(SOVA) is a turbo decoding algorithm that is suitable for hardware implementation. But its performance is not so good as maximum a posterior probability(MAP) algorithm. So it is very important to improve its performance. The non-correlation between minimum and maximum likelihood paths in SOVA is analyzed. The metric difference of both likelihood paths is used as iterative soft information, which is not the same as the traditional SOVA. The performance of the proposed SOVA is demonstrated by the simulations. For 1024-bit frame size and 9 iterations with signal to noise ratio from 1dB to 4dB, the experimental results show that the new SOVA algorithm obtains about more 0.4dB and 0.2dB coding gains more than the traditional SOVA and Bi-SOVA algorithms at bit error rate(BER) of 1×10~ -4 , while the latency is only half of the Bi-direction SOVA decoding.     

上行空时分组编码多载波码分多址系统的逐级干扰对消接收机算法

针对空时分组编码多载波码分多址系统的上行物理链路,提出了基于QR分解和基于最小均方误差的逐级干扰对消接收机算法。经算法处理后的数据矩阵保持了空时分组编码的正交结构,从而可以通过简单的线性处理实现空时分组编码的次优译码。与传统的置零接收机算法相比,此算法不会对接收机端的白噪声产生放大作用。计算机仿真结果表明,在独立衰落信道或相关衰落信道下,此算法均优于置零接收机算法。在误码率为10-6水平下,此算法比传统算法的信噪比改善约4dB。     

基于迭代处理的PCMA混合信号解调/译码算法

针对成对载波多址信号的分离,在实现信道参数估计且完成干扰抵消的基础上,该文利用信道编码信息提出一种联合线性最小均方误差(Minimum Mean-Square Error, MMSE)均衡和软译码的迭代解调/译码算法。该算法在均衡过程中利用译码后反馈的先验统计量来改善解调性能,重点研究了均衡与译码间的信息交互以及参数估计误差对解调性能的影响。仿真结果表明,对子码为(64,57,4)扩展BCH码的Turbo乘积码(Turbo Product Codes, TPC),采用QPSK调制且误比特率为10-3时,经过2次迭代能获得近4 dB的信噪比增益;采用8PSK调制且Es/N0大于20 dB时,经过2次迭代能将误比特率至少提升2个数量级。     

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm² area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.     

Trellis‐Based Decoding of High‐Dimensional Block Turbo Codes

This paper introduces an efficient iterative decoding method for high‐dimensional block turbo codes. To improve the decoding performance, we modified the soft decision Viterbi decoding algorithm, which is a trellis‐based method. The iteration number can be significantly reduced in the soft output decoding process by applying multiple usage of extrinsic reliability information from all available axes and appropriately normalizing them. Our simulation results reveal that the proposed decoding process needs only about 30% of the iterations required to obtain the same performance with the conventional method at a bit error rate range of 10^?5 to 10^?6.     

An analysis of the block error probability performance of iterative decoding

Asymptotic iterative decoding performance is analyzed for several classes of iteratively decodable codes when the block length of the codes N and the number of iterations I go to infinity. Three classes of codes are considered. These are Gallager's regular low-density parity-check (LDPC) codes, Tanner's generalized LDPC (GLDPC) codes, and the turbo codes due to Berrou et al. It is proved that there exist codes in these classes and iterative decoding algorithms for these codes for which not only the bit error probability P/sub b/, but also the block (frame) error probability P/sub B/, goes to zero as N and I go to infinity.     

LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low‐density parity‐check (LDPC) codes. An enhanced sum–product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error‐correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of 10^?8. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.     

Partitioned scheduling for sphere decoding with runtime constraints for practical MIMO communication systems

This paper presents an effective scheduling scheme for sphere decoding (SD) with runtime constraints, targeting the practical multiple‐input multiple‐output (MIMO) communication systems where neither the interleaving scheme nor its block size cannot be designed freely. The proposed scheme imposes runtime constraints on SD to distribute the errors due to the early termination of SD. Because the distributed errors may be corrected effectively by forward error correction, the error‐rate performance can be improved; experimental results show that the performance improvement is approximately 2dB in terms of the signal‐to‐noise ratio to achieve a bit‐error rate of 10^?4 in 4 × 4 16‐QAM MIMO systems. Copyright © 2015 John Wiley & Sons, Ltd.     

空间耦合LDPC码在AWGN信道下的性能分析

空间耦合LDPC(Spatially Coupled LDPC,SC-LDPC)码由于阈值饱和特性,被证明是未来无线通信系统的有力候选码型。SC-LDPC码是一种卷积LDPC码,在二元无记忆对称信道下采用置信传播译码算法时具有逼近香农限的性能。对SC-LDPC码的构造及其经典的置信传播译码算法进行了阐述,并在加性高斯白噪声信道下进行了性能仿真和分析。仿真结果表明,SC-LDPC码的约束长度越长或最大迭代次数越大,其性能就越逼近香农容量限。SC-LDPC码在误码率为10-5、最大迭代次数为100时,码长20000比码长10000大约有0.68 dB的增益;在误码率为10-5、码长为10000时,最大迭代次数100的SC-LDPC码比最大迭代次数10的码大约有0.66 dB的增益。仿真结果有效验证了SCLDPC码在无线通信系统中的良好性能。     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

The successively temporal error concealment algorithm using error-adaptive block matching principle

Generally, the temporal error concealment (TEC) adopts the blocks around the corrupted block (CB) as the search pattern to find the best-match block in previous frame. Once the CB is recovered, it is referred to as the recovered block (RB). Although RB can be the search pattern to find the best-match block of another CB, RB is not the same as its original block (OB). The error between the RB and its OB limits the performance of TEC. The successively temporal error concealment (STEC) algorithm is proposed to alleviate this error. The STEC procedure consists of tier-1 and tier-2. The tier-1 divides a corrupted macroblock into four corrupted 8 × 8 blocks and generates a recovering order for them. The corrupted 8 × 8 block with the first place of recovering order is recovered in tier-1, and remaining 8 × 8 CBs are recovered in tier-2 along the recovering order. In tier-2, the error-adaptive block matching principle (EA-BMP) is proposed for the RB as the search pattern to recover remaining corrupted 8 × 8 blocks. The proposed STEC outperforms sophisticated TEC algorithms on average PSNR by 0.3 dB on the packet error rate of 20% at least.     

A high-speed phosphorescent LED-based visible light communication system utilizing SQGNRC precoding technique

Peak-over-average power ratio (PAPR) control utilizing precoding technique based on square root-generalized raised cosine function is proposed and verified experimentally through a visible light communication system employing phosphor-based white light-emitting diodes for the first time. The simulation results show that the improved precoding matrix can further reduce PAPR by nearly 1 dB compared with existing precoding matrix based on square root raised cosine function and significantly achieve 3.5 dB improvement in contrast to original signals without precoding. The experimental result also proves that the bit error rate performance can be effectively improved by 1.62 dB at the same bandwidth and 0.76 dB at the same raw data rate in terms of quality factor when proposed precoding technique is applied, which clearly demonstrates its benefit and feasibility.     

一种低迭代次数的极化码置信传播译码算法

针对置信传播(Belief Propagation,BP)译码算法在迭代次数较多时吞吐量和译码时延性能提升受限的问题,提出了一种低迭代次数的极化码BP译码算法,通过采用比特翻转和子信道冻结的方式,降低译码过程中的迭代次数.仿真结果表明,相对于传统极化码BP译码算法(设置最大迭代次数为40次),所提算法在信噪比为3 dB时可将平均迭代次数减少约53％,处理单元平均计算次数减少约68％.该算法所带来的低时延和低功耗效益可运用在对功耗要求较高的大规模机器类型通信,以及对时延要求较高的超可靠低延迟通信等5G场景下的极化码译码中.     

空间耦合LDPC码的分层译码算法

针对长码长空间耦合低密度奇偶校验(SC-LDPC)码译码时延较长的问题,该文提出了分层滑动窗译码(LSWD)算法。该算法利用SC-LDPC子码码块的准循环特性和滑动窗内校验矩阵的层次结构,通过在滑动窗内对校验矩阵进行分层处理,优化层与层之间消息传递,从而加快窗内译码的收敛速度,减少了译码迭代次数。仿真和分析结果表明:在相同的信噪比(SNR)条件和相同的误码性能要求下,LSWD算法所需的迭代次数少于滑动窗译码(SWD)算法,特别在高信噪比下,LSWD算法的迭代次数约为SWD算法的一半,从而有效缩短全局译码时延;在相同译码迭代次数下,LSWD算法的译码性能优于SWD算法,而其计算复杂度增加不大。     

Bidirectional breadth-first algorithms for the decoding ofconvolutional codes

Bidirectional multiple-path tree searching algorithms for the decoding of convolutional codes are presented. These suboptimal coding algorithms use a multiple-path breadth-first bidirectional tree exploration procedure and long-memory convolution codes. It is shown that, compared to the usual M-algorithm, the bidirectional exploration considerably reduces the bit error propagation due to correct path loss. Computer simulations using rate-1/2 codes over binary symmetric channels are used to analyze the effect of the number of path extensions, code memory, and frame length on the bit error probability. The results show that with a bit error probability of 10^-5, coding gains on the order of 2 dB over the M-algorithm and 1 dB over a Viterbi decoder of equivalent complexity can be achieved     

低复杂度的TBCC自适应循环VA译码算法

咬尾是一种将卷积码转换为块码的技术,它消除了归零状态所造成的码率损失,同时避免了截尾带来的性能降低,在短块编码中具有明显优势。针对咬尾卷积码(TBCC)现有译码算法复杂度过大和收敛性问题,提出一种低复杂度的TBCC自适应循环维特比(VA)译码算法。该算法根据信道变化自适应调整译码迭代次数,使咬尾路径收敛到最佳。通过仿真对比不同译码算法的块错误率和译码迭代次数,结果表明TBCC性能明显好于传统卷积码;相比于同类循环VA算法,在不降低性能的前提下,改进算法简化了停止规则,减少译码迭代次数和复杂度,在低信噪比时,改进算法比传统绕维特比译码算法(WAVA)平均迭代次数减少约4次。      

一种面向物联网的轻量级增强型长距离物理层设计方法

为了提高LoRa在衰落信道下的误码率性能,该文设计了一种轻量级的增强型长距离(EnLoRa)物理层。首先,采用循环码移位键控(CCSK)作为纠错码,级联对角矩阵交织和啁啾扩频(CSS)调制技术,构造了一种新的比特交织编码调制(BICM)结构。然后,基于该结构,提出了一种基于比特对数似然比信息的软CSS解调和软译码算法,并将译码输出后的外信息作为先验信息反馈至解调模块,进行迭代译码。仿真结果表明,与相同码率的LoRa系统对比,EnLoRa系统在高斯信道下的编码增益提高了0.8 dB,在瑞利信道下的编码增益提高了7 dB。在此基础之上,通过多次迭代译码,还可以获得最大2.5 dB的额外收益。时间复杂度增加不到10%,空间复杂度增幅可忽略不计。该方法可望进一步降低物联网节点的功耗,在室内、市区和工业等复杂多径场景具有较大的应用价值。     

Multilevel block codes for Rayleigh-fading channels

New multilevel block codes for Rayleigh-fading channels are presented. At high signal-to-noise ratios (SNRs), the proposed block codes can achieve better bit error performance over TCM codes, optimum for fading channels, with comparable decoder complexity and bandwidth efficiency. The code construction is based on variant length binary component block codes. As component codes for the 8-PSK multilevel block construction, the authors propose two modified forms of Reed-Muller codes giving a good trade-off between the decoder complexity and the effective code rates. Code design criteria are derived from the error performance analysis. Multistage decoding shows very slight degradation of bit error performance relative to the maximum likelihood algorithm     

一种基于分段CRC码级联Hash极化码的设计

极化码作为一种线性分组码，具有较低的编码复杂度和确定的构造，但当其为中短码长时，性能会有所降低。提出一种基于分段循环冗余校验（cyclic redundancy check，CRC）码级联Hash极化码的设计方法，该方法在原有Hash极化码（Hash-Polar）的基础上，采用CRC分段校验进行双校验，分段CRC码在译码过程中能辅助路径度量，即对译码路径进行修饰，以此提高路径选择的可靠性，提高性能；另外，分段校验是将校验码分散地添加到输入的信息序列中，译码时对于CRC不通过的情况，可提前终止译码路径以省去不必要的译码计算量。最后，译码结束时，Hash校验码对修饰后的L条路径进行校验，选出最佳译码路径。仿真结果表明，所提出的设计方法比 CRC 辅助的 Hash 极化码（Hash-CRC-Polar）误码性能更优异。在高斯信道下，当码长为 128 bit、码率为 1/2、误码率为 10^-3时，所提出的基于分段 CRC 校验码的 Hash 极化码比Hash-CRC-Polar获得了约0.25 dB的增益。     

一种基于增强奇偶校验码级联极化码的新型编译码方法

极化码作为一种纠错码,具有较好的编译码性能,已成为5G短码控制信道的标准编码方案。但在码长较短时,其性能不够优异。提出一种基于增强奇偶校验码级联极化码的新型编译码方法,在原有的奇偶校验位后设立增强校验位,对校验方程中信道可靠度较低的信息位进行双重校验,辅助奇偶校验码在译码过程中对路径进行修剪,以此提高路径选择的可靠性。仿真结果表明,在相同信道、相同码率码长下,本文提出的新型编译码方法比循环冗余校验(cyclic redundancy check,CRC)码级联极化码、奇偶校验(parity check,PC)码级联极化码误码性能更优异。在高斯信道下,当码长为128、码率为1/2、误码率为10-3时,本文提出的基于增强PC码级联的极化码比PC码级联的极化码获得了约0.3 dB增益,与CRC辅助的极化码相比获得了约0.4 dB增益。