Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals

A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-/spl mu/m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.     

一种低压改进型MOS电荷泵电路的设计

针对使用标准CMOS技术实现的传统电荷泵输出电压较低的不足,文中提出将基本的电荷转移开关进行改进的MOS电荷泵,在泵送增益增加电路的基础上,通过在泵的输出级增加第3个控制信号来提高电荷泵的电压增益,以得到更高的输出电压,将其作为无线传感器的能量收集电路。仿真结果表明,该改进型电荷泵电路适合于低电压设备,并具有较高的泵送增益。其输出电压在同类电荷泵中最高,在1.5 V电源条件下,可高达8.5 V。     

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input–output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.     

An Output Buffer for 3.3-V Applications in a 0.13-μm 1/2.5-V CMOS Process

With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13-mum CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer has been fabricated in a 0.13-mum 1/2.5-V 1P8M CMOS process with Cu interconnects. The experimental results have confirmed that the proposed output buffer can be successfully operated at 133 MHz without suffering high-voltage gate-oxide overstress in the 3.3-V interface. In addition, a new level converter that is realized with only 1- and 2.5-V devices that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is also presented in this paper. The experimental results have also confirmed that the proposed level converter can be operated correctly     

一种适用于MEMS麦克风的新型恒压电荷泵设计

实现了一种新型恒压输出电荷泵电路,通过选择合理的电荷泵结构能有效抑制反向电流及衬底电流,并通过一种负反馈稳压电路得到低纹波且不随电源电压变化的稳压输出,非常适用于MEMS麦克风。该电路采用MIXIC0.35μm标准CMOS工艺实现,测试结果表明该电路能自适应2.8～3.6V的电源电压变化,输出稳定的9V直流电压。     

Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology

In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to provide higher operating speed with lower power supply voltage. However, regarding compatibility with the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability problems in the interface circuits due to the voltage levels higher than normal supply voltage (1$,times,$ VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tolerant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability issues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications.      

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

A dual-phase charge pump circuit with compact size

In this paper, a regulated dual-phase charge pump with compact size is presented. By means of a nano-ampere switched-capacitor voltage reference (SCVR) circuit, the dual-phase charge pump regulator can reduce the quiescent current and the output ripple. Besides, a new power stage is proposed to define the stability of the overall system. Owing to the design of buffer stage, the charge pump regulator can extend bandwidth and increase phase margin. Thus, the transient response and driving capability can be improved. Beside, the proposed automatic body switching circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. This chip was fabricated by TSMC 0.35 μm, 3.3 V/5 V 2P4 M CMOS technology. The input voltage range varies from 2.9 to 4.9 V for the lithium battery and the output voltage is regulated at 5 V. Experimental results demonstrate the charge pump can provide 50 mA maximum load current without any oscillation problems.     

Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors

Overview on the prior designs of the mixed-voltage I/O buffers is provided in this work. A new 2.5/5-V mixed-voltage I/O buffer realized with only thin gate-oxide devices is proposed. The new proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-$mu$m CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this work. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers can be easily scaled toward 0.18-$mu$m (or below) CMOS processes to serve other mixed-voltage I/O interfaces, such as 1.8/3.3-V interface.     

MOS charge pumps for low-voltage operation

New MOS charge pumps utilizing the charge transfer switches (CTSs) to direct charge flow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTSs can eliminate the reverse charge sharing phenomenon and further improve the voltage pumping gain. The limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude. Using the new circuit techniques, a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump are demonstrated     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

一种高性能鉴频鉴相器的设计

分析了电荷泵型锁相环中鉴相器和电荷泵的非理想因素及优化设计方法。基于台积电公司(TSMC)0.35μm 2层多晶硅4层金属(2P4M)CMOS工艺,设计了一种低杂散的鉴频鉴相器结构,该结构通过"自举"的方法,用单位增益放大器使充放电前后开关管各节点处的电压保持不变,从而消除了电荷共享的影响,减小了鉴相器的输出杂散。仿真结果表明相比于传统鉴相器结构,该鉴频鉴相器有效抑制了电荷共享问题,电荷泵开关管开启时的充放电电流尖峰大大减小了,鉴相前后的电压波动小于200μV,脉冲尖峰仅为3.07 mV,有效降低了鉴频鉴相器的输出杂散。     

一种应用于MEMS麦克风偏置电路的电荷泵设计

MEMS麦克风需要一个高于10 V的偏置电压才能工作,这个高电压一般由内部电荷泵电路产生.在传统Dickson电荷泵结构的基础上,提出一种改进的电荷泵结构.它首先将非重叠时钟的幅度加倍,然后用幅度加倍的时钟作为电荷泵的驱动时钟,取得了明显的升压效果.Hspice仿真结果表明,电源电压为1.4V时,6级二极管-电容升压单元就可以实现10.7674 V的输出电压.与传统的Dickson升压电路相比,改进型电荷泵的升压单元减少了4级,且其核心部分的面积减小了21％,功耗降低了40％(参考SMIC 0.35 μm CMOS工艺).     

Low-Ripple and Dual-Phase Charge Pump Circuit Regulated by Switched-Capacitor-Based Bandgap Reference

This paper proposes a low-ripple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference. Due to design of a buffer stage, a system can have better bandwidth and phase margin, and thus, the transient response and driving capability can be improved. Besides, the dual-phase control can reduce the output voltage ripple by means of only one closed-loop regulation in order to improve the power conversion efficiency. Besides, the proposed automatic body switching (ABS) circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. Usually, the regulated charge pump circuit needs a bandgap reference circuit to provide a temperature-independent reference voltage. The switched-capacitor-based bandgap reference circuit is utilized to regulate the output voltage. This chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 mum 3.3 V/5 V 2P4M CMOS technology. The input voltage range varies from 2.9 to 5.5 V, and the output voltage is regulated at 5 V. Experimental results demonstrate that the charge pump can provide 48 mA maximum load current without any oscillation problems.     

A regulated charge pump with small ripple voltage and fast start-up

A regulated charge pump circuit is realized in a 3.3-V 0.13-/spl mu/m CMOS technology. The charge pump exploits an automatic pumping control scheme to provide small ripple output voltage and fast start-up by decoupling output ripple and start-up time. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. The former automatically adjusts the size of pumping driver to reduce ripple voltage according to output voltage. The latter changes the pumping period by controlling a voltage-controlled oscillator (VCO). The output frequency of the VCO varies from 400 kHz to 600 kHz by controlling the input bias voltage of the VCO. The prototype chip delivers regulated 4.5-V output voltage from a supply voltage of 3.3 V with a flying capacitor of 330 nF, while providing 30 mA of load current. The area is 0.25 mm/sup 2/ and the measured output ripple voltage is less than 33.8 mV with a 2-/spl mu/F load capacitor. The power efficiency is greater than 70% at the range of load current from 1 to 30 mA. An analytical model for ripple voltage and recovery time is proposed demonstrating a reasonable agreement with SPICE simulation results.