多阳极220 GHz倍频器单片设计

介绍了一款基于GaAs肖特基二极管单片工艺的220 GHz倍频器的设计过程以及测试结果。为提高输出功率,倍频器采用多阳极结构,8个二极管在波导呈镜像对称排列,形成平衡式倍频器结构。采用差异式结电容设计解决了多阳极结构端口散射参数不一致问题,提高了倍频器的转换效率和工作带宽。对设计的倍频器进行流片、装配和测试,测试结果显示：倍频器在204~234 GHz频率范围内,转化效率大于15%;226 GHz峰值频率下实现最大输出功率为90.5 mW,转换效率为22.6%。设计的220 GHz倍频器输出功率高,转化效率高,工作带宽大。     

Single-Gate MESFET Frequency Doublers

A simple analytic model of the FET frequency doubler is used to determine the relative contributions of the various nonlinearities to harmonic generation. FET doubler conversion gain and its variation with frequency relative to the fundamental frequency available gain is also estimated. Large-signal computer simulations are used to determine the validity of the analytic model and provide further information on conversion gain and its frequency dependence. The analytic and computer predictions are compared with experimental measurements on a 4- to 8-GHz single-gate FET frequency doubler.     

基于肖特基二极管的太赫兹二倍频器设计

固态倍频器是太赫兹源应用中的关键器件,如何利用非线性器件提高太赫兹倍频器件的效率是设计太赫兹固态电路的关键。本文介绍了利用肖特基二极管非线性特性设计固态太赫兹二倍频器的2种方法,即采用直接阻抗匹配和传输模式匹配设计了2种不同拓扑结构的170 GHz二倍频器,针对设计的结构模型,分别进行三维有限元电磁仿真和非线性谐波平衡仿真。仿真结果表明,在17 dBm输入功率的驱动下,倍频器在160 GHz~180 GHz输出频率范围内,倍频效率在15%左右,输出功率大于7 mW。最后对2种方法设计的倍频器结构进行了简单对比和分析,为今后太赫兹倍频研究和设计提供仿真方法。     

一种悬置微带毫米波倍频器

用国产封装型GaAs高优植变容二极管设计制作了一个毫米波二倍频器。倍频电路采用屏蔽悬置微带线结构来实现,整个电路印制在一块0.127mm厚的RT-Duroid5880软基片上。该倍频器具有结构新颖、简单,腔体加工容易等特点。最大倍频效率为15.9％,输出频率在2GHz的范围内,倍频效率大于10％。同时,设计了一种新型的波导到悬置微带线过渡型式,其设计思想可供设计某些不同传输线间的过渡时参考。     

Frequency mixer with a frequency doubler for integrated circuits

We have developed a bipolar LSI, including a frequency mixer and a local oscillator frequency doubler. The local oscillator frequency doubler consists of two identical unbalanced emitter-coupled pairs with a different emitter area ratio, whose input terminals are connected cross-coupled and whose output terminals are connected in parallel, and is coupled with the frequency mixer directly in the LSI. The fabricated LSI operates on supply voltage as low as 2.7, and has been put into practical use for a cordless telephone system     

The Design of Broad-Band Frequency Doublers Using Charge-Storage Diodes

Many frequency multipliers can be viewed as consisting of an impedance inverter which couples together impedances at two different frequencies. Using this point of view, the design, construction, and evaluation of a five-resonator, broad-band frequency doubler employing charge-storage diodes is discussed. The doubler is a balanced design, employing two diodes and a balun. Design procedures which relate a low-pass filter prototype to the doubler circuit are presented. Good agreement between theory and experiment has been demonstrated; the experimental doubler exhibits approximately an octave bandwidth at 50 percent efficiency with an input frequency range of 1 to 2 GHz.     

A 25–75 GHz Miniature Double Balanced Frequency Doubler in 0.18-$mu$m CMOS Technology

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm². To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.     

Analysis of balanced active doubler for broad-band operation - thefrequency-tuning concept

A comprehensive analysis of an active balanced frequency doubler is described and proposed as a new concept: tuning the center frequency at which the doubler exhibits its highest performance to extend the usable bandwidth of the device. The concept is validated using a fabricated V-band pseudomorphic high electron-mobility transistor frequency doubler. For this device, a substantial improvement in the usable bandwidth (more than double) is achieved, demonstrating that the proposed concept is particularly suitable for the realization of high spectral purity and widely tunable V-band frequency sources     

A 3–50 GHz Ultra-Wideband PHEMT MMIC Balanced Frequency Doubler

A novel configuration of ultra-wideband (UWB) GaAs PHEMT monolithic microwave integrated circuit balanced frequency doubler is presented. By using two different terminal impedances of the common-source/common-gate active balun, the doubler exhibits UWB characteristic with more than a four octave frequency range. From 3 to 50 GHz, the measured conversion gain and fundamental frequency suppression of the doubler are better than $-4$ dB and 15 dB.      

Digital Frequency Multipliers Using Multisection Two-Strip Coupled Line

This paper describes new networks which acts as digital frequency multipliers such as doubler, tripler, and so on for input clock frequency. The networks consist of cascaded sections of uniform lossless commensurate coupled-transmission-lines and three resistors of II-structure, and the proposed multipliers are quite new in the sense of being built without using active or nonlinear circuit elements. The theoretical and experimental results for a coupled-line digital frequency doubler are compared and found to be in good agreement.     

一种超宽带毫米波倍频器设计

叙述了一种超宽带毫米波倍频器的设计,该倍频器由有源差分balun级、对管倍频级和分布式功率放大级三个部分组成。在30—50GHz输出频率范围内,倍频器具有5dB的变频增益,输出功率大于13dBm,基波抑制大于15dB。     

340 GHz GaN大功率固态倍频链

随着太赫兹技术的应用和发展,对大功率太赫兹固态源的需求愈加迫切。文中基于GaN肖特基二极管(SBD)工艺设计并制造了具有高功率输出的170 GHz和340 GHz太赫兹倍频器,实现了340 GHz大功率太赫兹固态倍频链。采用多管芯GaN SBD提高器件功率承载能力,综合开展电路优化设计提升倍频性能,通过仿真研究和实验测试,验证了倍频器设计的有效性和先进性。170 GHz倍频器的实测峰值输出功率达到580 mW,倍频效率为14.5%。340 GHz倍频器的实测峰值输出功率为66 mW,倍频效率为12.5%。该太赫兹固态倍频链性能优良,在太赫兹系统中具有重要的应用价值。     

An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp

This paper presents a switched-capacitor voltage doubler using pseudo-continuous control (PCC). The proposed PCC does not require extra power transistor to continuously regulate the output of the doubler, thereby saving chip area. The PCC also allows the doubler to operate at lower switching frequencies without sacrificing transient response. The light-load efficiency of the regulated doubler can thus be enhanced by reducing the switching power loss. In addition, a three-stage switchable opamp with time-multiplexed enhanced active-feedback frequency compensation is developed to implement the controller. The proposed implementation enhances the speed of the loop response and then improves the load transient response of the regulated doubler. The SC voltage doubler with the proposed PCC controller has been fabricated in a 0.6-mum CMOS process. The regulated doubler achieves >87% power efficiency even for the load current of 5 mA. By operating the doubler at switching frequency of 200 kHz and using a output capacitor of 2.2 muF, a maximum output ripple of 20mV is maintained for the load current changing from 50 mA to 150 mA. The output transient recovery time of the regulated doubler is ~25 mus with load-current step changes of 100 mA/1 mus     

A Novel Balanced MMIC Frequency Multiplier Configuration

A characterisation method, suitable for the study of balanced MMIC frequency multiplier circuits is presented. Using this approach, a number of frequency doubler and tripler configurations are considered. The influence of the non-ideal amplitude/phase balance characteristics of some planar hybrids on the harmonic rejection properties of these circuits is discussed. Optimum circuit configurations for doubler and tripler applications are proposed. Design details for a novel generalised configuration, which can be utilised for the balancing of single-ended multiplier circuits of any order, are outlined. The harmonic generation characteristics inherent in this approach are discussed.     

宽带巴伦二倍频器分析

本文给出各种宽带巴伦二倍频器的电路结构,提出用频域幂级数法分析这类倍频器的方法.定义出谐波矩阵及其算法,从而可以准确计算这类倍频器的特性.     

High-efficiency Q-to-W-band MIC frequency doubler

Integrated-circuit phase-lock oscillators are extremely difficult to develop above 60 GHz because of circuit losses. A viable alternative is to use a frequency doubler. A Q-to-W-band (40 to 80 GHz) frequency doubler has been developed using integrated-circuit suspended stripline. A conversion loss of less than 6.5 dB has been achieved with the output frequency at 80 GHz. This high efficiency was obtained by an innovative input and output matching circuit design. The advantages over a waveguide doubler include large reductions in size, weight and cost.     

2-20GHz宽带倍频器研究

研制了一种2～20GHz超宽带微波倍频器。该倍频器的核心是四只性能一致的肖特基势垒二极管形成的桥形堆,输入、输出电路则采用了适于宽带匹配的巴伦结构。在要求的频段范围内达到的指标：变频损耗优于15dB,典型值10dB;基波隔离优于25dB,典型值30dB;三次谐波抑制优于29dBc,典型值为35dBc。测试表明,该倍频器具有良好的可靠性和可重复性。     

基于肖特基变容二极管的0.17 THz 二倍频器研制

研制了一种基于肖特基变容二极管的0.17 THz 二倍频器, 该器件为0.34 THz 无线通信系统收发前端提供了低相噪、低杂散的本振信号.倍频器结构基于波导腔体石英基片微带电路实现, 其核心器件是多结正向并联的肖特基变容二极管.文中采用结参数模型和三维电磁模型相结合的方式对二极管进行建模, 通过两种电路匹配方式实现了0.17 THz 二倍频器的最优化设计, 最终完成器件的加工及测试.测试结果表明, 在输入80~86 GHz, 20 dBm 的驱动信号下, 倍频器的最大输出功率达12.21 mW, 倍频效率11%, 输出频点为163 GHz;当前端输入功率达到饱和状态时, 该频点输出功率可达21.41 mW.     

164-GHz MMIC HEMT doubler

In this paper, a MMIC frequency doubler based on an InP HEMT and grounded CPW (GCPW) technology is reported. The doubler demonstrated a conversion loss of only 2 dB and output power of 5 dBm at 164 GHz. The 3 dB output power bandwidth is 14 GHz, or 8.5%. This is the best reported result for a MMIC HEMT doubler above 100 GHz     

High-Frequency Doubler Operation of GaAs Field-Effect Transistors

A comprehensive study of single-gate GaAs FET frequency doublers is presented. Special emphasis is placed on exploring high-frequency limitations, while yielding explanations for previously observed lower frequency phenomena as well. Extensive Iarge-signal simulations demonstrate the underlying relationships between circuit performance characteristics and principal design parameter. Verifying experiments include straight frequency doubler and a self-oscillating doubler, both with output signal frequencies in Ku-band. The self-oscillating doubler appears especially attractive, yielding an overall dc-to-RF efficiency of 10 percent. The type of transistor employed in the numerical and experimental examples possesses a gate length of 0.5 µm and a gate width of 250 µm.