Futher Results on Rate 1/N Convolutional Code Constructions with Minimum Required SNR Criterion

New good(K, 1/N)convolutional codes for8 leq K leq 13and2 leq N leq 8were found and tabulated which require minimum signal-to-noise ratio (SNR) for given desired bit error rates (BER) with Viterbi decoding. The transfer function bound was used for the BER evaluations.     

Majority-logic-like decoding of vector symbols

The use of the structure of one-step decodable majority logic codes for enhanced and simplified vector symbol decoding, such as outer code decoding of concatenated codes, is proposed. For J equations checking a particular symbol, the technique to be described almost always corrects the symbol if there are J-1 or fewer symbol errors, and often corrects cases of far more than J symbol errors. Ordinarily, majority level decoding with J equations for a symbol corrects the symbol in all cases where there are up to [J/2] errors. The decoding power is comparable to Reed-Solomon codes, but decoding is simpler than for Reed-Solomon codes     

Majority logic decoding using combinatorial designs (Corresp.)

If the vectors of some constant weight in the dual of a binary linear code support a(nu,b,r,k,lambda)balanced incomplete block design (BIBD), then it is possible to correct[(r + 2 - 1)/2lambda]errors with one-step majority logic decoding. This bound is generalized to the case when the vectors of certain constant weight in the dual code support at-design. With the aid of this bound, the one-step majority logic decoding of the first, second, and third order Reed-Muller codes is examined.     

Sort-and-match algorithm for soft-decision decoding

Let a q-ary linear (n, k) code C be used over a memoryless channel. We design a decoding algorithm Ψ_N that splits the received block into two halves in n different ways. First, about √N error patterns are found on either half. Then the left- and right-hand lists are sorted out and matched to form codewords. Finally, the most probable codeword is chosen among at most n√N codewords obtained in all n trials. The algorithm can be applied to any linear code C and has complexity order of n³√N. For any N⩾q^n-k, the decoding error probability P_N exceeds at most 1+q^n-k/N times the probability P_Ψ (C) of maximum-likelihood decoding. For code rates R⩾1/2, the complexity order q^n-k/2 grows as square root of general trellis complexity q^min{n-k,k}. When used on quantized additive white Gaussian noise (AWGN) channels, the algorithm Ψ_N can provide maximum-likelihood decoding for most binary linear codes even when N has an exponential order of q^n-k     

Real-Domain Decoder for Full-Rate Full-Diversity STBC with Multidimensional Constellations

In this letter, we present a new maximum likelihood (ML) decoding algorithm for space time block codes (STBCs) that employ multidimensional constellations. We start with a lattice representation for STBCs which transforms complex channel models into real matrix equations. Based on the lattice representation, we propose a new decoding algorithm for quasiorthogonal STBCs (QO-STBC) which allows simpleML decoding with performance identical to the conventional ML decoder. Multidimensional rotated constellations are constructed for the QO-STBCs to achieve full diversity. As a consequence, for quasi-orthogonal designs with an arbitrary number of transmit antennas N (N ? 4), the proposed decoding scheme achieves full rate and full diversity while reducing the decoding complexity from ∂(M_c^N/2) to ∂(M_c^N/4) in a M_c-QAM constellation.     

光纤通道8B/10B编码的ASIC研究与设计

在目前的高速串行数据传输中广泛采用的是8B/10B编解码,为了达到简化实现结构,用于大规模集成电路的目的,研究了现有各种不同的8B/10B编解码的特点和内在相关性,并在此基础上介绍了用一种VHDL设计8B/1B编码逻辑描述的方法,将其设计成专用集成电路或嵌入到FPGA中,构成一个逻辑运算量小,速度快,可靠性高的IP核,最后给出在Altera公司软件平台Quartus Ⅱ上进行的EDA综合仿真结果。该测试结果为采用本方法设计不同速率的超高速编解码芯片奠定了基础。     

On low complexity stack decoding of convolutional codes

This article presents techniques for improving the distribution of the number of stack entries, for stack sequential decoding over a hard quantized channel, with emphasis on high rate codes. It is shown that, for a class of high rate b/(b+1) codes, a table-based true high rate approach can be easily implemented for obtaining a decoding advantage over the punctured approach. Modified algorithms, which significantly improve the distribution of the number of stack entries and decoding time, are proposed for rate 1/N codes and high rate b/(b+1) codes     

On algebraic decoding of the Z4-linear Goethals-likecodes

The Z₄-linear Goethals-like code of length 2^m has 2^2m+1-3m-2 codewords and minimum Lee distance 8 for any odd integer m⩾3. We present an algebraic decoding algorithm for all Z₄-linear Goethals-like codes C_k introduced by Helleseth et al.(1995, 1996). We use Dickson polynomials and their properties to solve the syndrome equations     

一种新的光纤通信8B/10B编解码实现方法研究

本文研究了8B／10B编码规则及其内在相关性，提出了一种查表和逻辑运算相结合的新的8B／10B编、解码方法，具有运算量小、编解码同步好、速度快、可靠性高等优点。该方法通过硬件描述语言Verilog HDL实现编解码算法的描述，并通过高性能的FPGA器件进行仿真和综合，实现了具体的硬件电路，并验证了设计方法的有效性和可行性。采用该方法可实现不同速率的高速8B／10B编解码模块或芯片的设计。     

Decoding of Expander Codes at Rates Close to Capacity

The decoding error probability of codes is studied as a function of their block length. It is shown that the existence of codes with a polynomially small decoding error probability implies the existence of codes with an exponentially small decoding error probability. Specifically, it is assumed that there exists a family of codes of length N and rate R=(1-epsiv)C (C is a capacity of a binary-symmetric channel), whose decoding probability decreases inverse polynomially in N. It is shown that if the decoding probability decreases sufficiently fast, but still only inverse polynomially fast in N, then there exists another such family of codes whose decoding error probability decreases exponentially fast in N. Moreover, if the decoding time complexity of the assumed family of codes is polynomial in N and 1/epsiv, then the decoding time complexity of the presented family is linear in N and polynomial in 1/epsiv. These codes are compared to the recently presented codes of Barg and Zemor, "Error Exponents of Expander Codes", IEEE Transactions on Information Theory, 2002, and "Concatenated Codes: Serial and Parallel", IEEE Transactions on Information Theory, 2005. It is shown that the latter families cannot be tuned to have exponentially decaying (in N) error probability, and at the same time to have decoding time complexity linear in N and polynomial in 1/epsiv     

On the Logical Computational Complexity Analysis of Turbo Decoding Algorithms for the LTE Standards

Evaluating the computational complexity of decoders is a very important aspect in the area of Error Control Coding. However, most evaluations have been performed based on hardware implementations. In this paper, different decoding algorithms for binary Turbo codes which are used in LTE standards are investigated. Based on the different mathematical operations in the diverse equations, the computational complexity is derived in terms of the number of binary logical operations. This work is important since it demonstrates the computational complexity breakdown at the binary logic level as it is not always evident to have access to hardware implementations for research purposes. Also, in contrast to comparing different Mathematical operations, comparing binary logic operations provides a standard pedestal in view to achieve a fair comparative analysis for computational complexity. The usage of the decoding method with fewer number of binary logical operations significantly reduces the computational complexity which in turn leads to a more energy efficient/power saving implementation. Results demonstrate the variation in computational complexities when using different algorithms for Turbo decoding as well as with the incorporation of Sign Difference Ratio (SDR) and Regression-based extrinsic information scaling and stopping mechanisms. When considering the conventional decoding mechanisms and streams of 16 bits in length, Method 3 uses 0.0065% more operations in total as compared to Method 1. Furthermore, Method 2 uses only 0.0035% of the total logical complexity required with Method 1. These computational complexity analysis at the binary logical level can be further used with other error correcting codes adopted in different communication standards.

     

Single-carrier space-time block-coded transmissions over frequency-selective fading channels

We study space-time block coding for single-carrier block transmissions over frequency-selective multipath fading channels. We propose novel transmission schemes that achieve a maximum diversity of order N/sub t/N/sub r/(L+1) in rich scattering environments, where N/sub t/ (N/sub r/) is the number of transmit (receive) antennas, and L is the order of the finite impulse response (FIR) channels. We show that linear receiver processing collects full antenna diversity, while the overall complexity remains comparable to that of single-antenna transmissions over frequency-selective channels. We develop transmissions enabling maximum-likelihood optimal decoding based on Viterbi's ( 1998) algorithm, as well as turbo decoding. With single receive and two transmit antennas, the proposed transmission format is capacity achieving. Simulation results demonstrate that joint exploitation of space-multipath diversity leads to significantly improved performance in the presence of frequency-selective fading channels.     

Fast adaptive arithmetic code for large alphabet sources with asymmetrical distributions

We address the problem of constructing an adaptive arithmetic code in the case where the source alphabet is large and there are lots of different symbols with equal counts of occurrence. For an alphabet of N symbols and r distinct symbol weights we describe a code for which the number of operations needed for encoding and decoding is equal to clogr+c/sub 1/ instead of clogN+c/sub 2/ as in previous arithmetic codes, c, c/sub 1/, c/sub 2/ are constants. When r is small relative to N-which is the case for most practical coding problems on large alphabets-the encoding and decoding speed of the suggested code will be substantially greater than with known methods.     

Generalized threshold decoding of linear codes

It is proved that every linear code of dimensionkcan be decoded by a threshold decoding circuit that is guaranteed to correcteerrors ife leq (d - 1)/2wheredis the minimum distance of the code. Moreover it is demonstrated that the number of levels of threshold logic is less than or equal tokby giving an algorithm for generating the decoding logic employingklevels.     

8B/10B编解码的IP核设计

研究了8B/10B编码的编码特点和内在相关性,并在此基础上介绍了一种用Verilog HDL设计8B/10B编解码逻辑描述的方法,将其嵌入到FPGA中或设计成ASIC,可构成一个资源使用少、速度快、可靠性高的IP核.文中着重介绍8B/10B编解码总体设计方案,详细描述其内部工作原理和实现.最后给出在Altera公司软件平台QuartusⅡ上进行EDA的综合和仿真结果.     

High-speed 8:1 multiplexer and 1:8 demultiplexer implemented withAlGaAs/GaAs HBTs

An 8:1 multiplexer (MUX) and 1:8 demultiplexer (DMUX) implemented with AlGaAs/GaAs heterojunction bipolar transistors are described. The circuits were designed for lightwave communications, and were demonstrated to operate at data rates above 6 Gb/s. These are among the fastest 8-b MUX-DMUX circuits ever reported. Each contains about 600 transistors and consumes about 1.5 W. The pair provides features such as resettable timing, data framing, and clock recovery circuitry, and a built-in decision circuit on the DMUX. Emitter-coupled logic (ECL) compatible input/output (1/O) signals are available. The circuits were implemented with bi-level current mode logic (CML) and require a -5.2-V power supply and a +1-V bias for ECL compatibility     

On algebraic soft-decision decoding algorithms for BCH codes

Three algebraic soft-decision decoding algorithms are presented for binary Bose-Chaudhuri-Hocquengham (BCH) codes. Two of these algorithms are based on the bounded distance (BD)+1 generalized minimum-distance (GMD) decoding presented by Berlekamp (1984), and the other is based on Chase (1972) decoding. A simple algebraic algorithm is first introduced, and it forms a common basis for the decoding algorithms presented. Next, efficient BD+1 GMD and BD+2 GMD decoding algorithms are presented. It is shown that, for binary BCH codes with odd designed-minimum-distance d and length n, both the BD+1 GMD and the BD+2 GMD decoding algorithms can be performed with complexity O(nd). The error performance of these decoding algorithms is shown to be significantly superior to that of conventional GMD decoding by computer simulation. Finally, an efficient algorithm is presented for Chase decoding of binary BCH codes. Like a one-pass GMD decoding algorithm, this algorithm produces all necessary error-locator polynomials for Chase decoding in one run     

Superimposed codes based on punctured convolutional codes

Punctured convolutional codes of rates k₁/n and k₂ /n are applied to |u|u+v construction, and then a superimposed code of rate (k₁+k₂)/(2n) is constructed. A suboptimal decoding procedure is presented for the superimposed codes, and it reduces the decoding complexity as compared with maximum likelihood decoding for the known convolutional codes     

A 5-ns 1-Mb ECL BiCMOS SRAM

A 1-Mword×1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8-μm BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm×6.7 mm and 8.5 μm×5.3 μm, respectively. The active power is 1 W at 100-MHz operation     

High rate convolutional codes with good distance profiles (Corresp.)

The result of a computer search for systematic convolutional codes with rates(N - 1)/NforNfrom 3 to 8 is presented. The codes have rapidly growing column distance, making them attractive for sequential decoding.