Quadded NOR Logic

Quadded Logic, a technique for the introduction of redundancy to digital systems, allows a number of component failures to occur in the system without disturbing its capacity to perform the function for which it was designed. This paper describes quadded logic using the NOR gate as the basic building block. A reliability prediction technique is shown with which the performance of this redundancy scheme can be evaluated. The gains in reliability possible through the use of quadding depend on the reliability of the nonredundant gates that make up the redundant stage. Where these gates are already very reliable, the probability of failure of the NOR function can be reduced by several orders of magnitude.     

Computer Redundancy: Design, Performance, and Future

The literature on the theoretical aspects of redundancy in digital computers is extensive providing a sound basis for highly reliable design. This paper describes the design problems, the reliability prediction, the field performance, and the future application of redundancy techniques to digital systems. Triple modular redundancy (TMR) is described using the logic of the Launch Vehicle Digital Computer utilized in the uprated Saturn I and the Saturn V vehicles. The self-correcting memory of this computer is described along with the associated design problems and the design verification based on production experience. Consideration is given to system design problems involved with TMR logic. A Monte Carlo technique for predicting computer reliability is considered in a design engineering rather than programmer approach. The unique means of indicating single-channel malfunctions, while continuing to mask these single-channel malfunctions with respect to system operation, is introduced. The result of field operation are given and compared with predicted reliability. Quad redundancy at the component part level is described using the circuitry of the primary processor and data storage (PPDS) for NASA's Orbital Astronomical Observatory. The process of arriving at a quad redundancy implementation is considered in light of the constraints of cost, schedule, and an initial reliability requirement of 95 percent for a year's operation in space. The circuit and system design problems associated with quad redundancy such as impedance and part parameter variations, power consumption, fan out limitations, and testing restrictions are indicated. The results of field operation are given and compared with predicted reliability.     

An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction

SRAM based FPGA are subjected to ion radiation in many operating environments. Following the current trend of shrinking device feature size & increasing die area, newer FPGA are more susceptible to radiation induced errors. Single event upsets (SEU), (also known as soft-errors) account for a considerable amount of radiation induced errors. SEU are difficult to detect & correct when they affect memory-elements present in the FPGA, which are used for the implementation of finite state machines (FSM). Conventional practice to improve FPGA design reliability in the presence of soft-errors is through configuration memory scrubbing, and through component redundancy. Configuration memory scrubbing, although suitable for combinatorial logic in an FPGA design, does not work for sequential blocks such as FSM. This is because the state-bits stored in flip-flops (FF) are variable, and change their value after each state transition. Component redundancy, which is also used to mitigate soft-errors, comes at the expense of significant area overhead, and increased power consumption compared to nonredundant designs. In this paper, we propose an alternate approach to implement the FSM using synchronous embedded memory blocks to enhance the runtime reliability without significant increase in power consumption. Experiments conducted on various benchmark FSM show that this approach has higher reliability, lower area overhead, and consumes less power compared to a component redundancy technique.     

高速ATM中CRC算法与信元定界的FPGA实现

在通信领域循环冗余码CRC得到了广泛的应用。为解决高速ATM中信头误码差错控制和信元定界问题,通过对循环冗余校验原理的分析,采用递推的方法得出了一种高效的CRC算法。该算法能检测到多个bit错误,并能纠正单bit的错误。相对于一般的按位串行计算或者查表并行计算的方法,这种算法运算速度快且不需要额外的空间存储余数表,提高了高速链路上数据吞吐率。数据之间逻辑关系简单,十分便于采用FPGA实现。     

Two effective methods to mitigate soft error effects in SRAM-based FPGAs

This paper proposes an effective architecture that can mitigate Single Event Upset (SEU) effects in SRAM-based FPGAs. The architecture employs two different methods in both logic and interconnection resources. The logic resources utilize a new function generator that can tolerate 100% of single faults in its configuration memory while it can generate all the k-input Boolean functions. In the interconnection resources, a kind of formation redundancy that can detect 94% of single faults in its configuration memory is applied. Both methods are based on an interesting relation in Boolean functions, identified as mapping. By this concept, a Boolean function is generated by modifying the inputs of other Boolean functions. The effectiveness of the proposed architecture is procured by a standard fault injection tool; moreover, different parameters such as required area, power, and delay are achieved by using synopsis® synthesis tool. The results show that the area, power, and delay overheads are respectively 179%, 94%, and 60% in comparison with the simple architecture.     

An efficient management scheme for updating redundant information in flash-based storage system

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as a storage media in embedded and computer system environments. However, there are many shortcomings in flash memory such as potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To address these performance and reliability anomalies, many large-scale storage systems use redundancy-based parallel access schemes such as RAID techniques. However, such redundancy-based schemes incur high overhead due to generating and storing redundancy information, especially in flash-based storage systems. In this paper, we propose a novel and performance-effective approach using a redundancy-based data management scheme in flash storage, called Flash-aware Redundancy Array. The proposed technique not only reduces the redundancy management overhead by performing redundancy update operations during idle periods, but also provides a preventive mechanism to recover data from unexpected read errors occurring before such redundancy update operations finish. From the experiments, we found that the proposed technique improves flash-based storage systems by 19% in average execution time as compared to other redundancy-based approaches.     

Enhanced FPGA reliability through efficient run-time faultreconfiguration

The expanded use of field programmable gate arrays (FPGA) in remote, long life, and system-critical applications requires the development and implementation of effective, efficient FPGA fault-tolerance techniques. FPGA have inherent redundancy and in-the-field reconfiguration capabilities, thus providing alternatives to standard integrated circuit redundancy-based fault-recovery techniques. Runtime reliability can be enhanced by using such unique features. Recovery from permanent logic and interconnect faults without runtime computer-aided design (CAD) support can be efficiently performed with the use of fine-grained and physical design partitioning. Faults are localized to small partitioned blocks that have fixed interfaces to the surrounding portions of the design, and the affected blocks are reconfigured with previously generated, functionally equivalent block instances that do not use the faulty resources. This technique minimizes the post-fault-detection system downtime, while requiring little area overhead. Only the finely located faulty portions of the FPGA are removed from use. In addition, the end user need not have access to CAD tools, making the algorithm completely transparent to system users. This approach has been efficiently implemented on a diverse set of FPGA architectures. The algorithm's flexibility is also apparent from the variable emphases that can be placed on system reliability, area overhead, timing overhead, design effort, and system memory. Given user-defined emphases, the algorithm can be modified to specific application requirements. Experiments using random s-independent and s-correlated fault models reveal that the approach enhances system reliability, while minimizing area and timing overhead     

软件错误检测与纠正技术可靠性研究

基于信息冗余的错误检测与纠正（Error Detection and Correction,EDAC）技术是常见的系统级抗单粒子翻转（Single Event Upsets,SEU）的容错方法,软件实现的EDAC技术是硬件EDAC技术的替代方案,通过软件编程,在现有存储段上增加具有纠错功能的编码（Error-correcting Codes,ECC）来实现存储区错误的检测和纠正。分析了软件EDAC方案中,纠错编码的纠错能力及编码效率、刷新间隔、需保护代码量等因素对可靠性的影响,分析和仿真实验结果表明,对于单个粒子引起的存储器随机错误,提高单个码字的纠错能力及编码效率、增大刷新间隔对可靠性的影响不大,而通过缩短任务执行的代码量来提高刷新间隔,以及压缩需保护代码的总量,对可靠性有较大改进。分析结论能够指导工程实践中,在实现资源、实时性、可靠性之间进行优化选择。      

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

A multistrata dynamic random access memory (DRAM) vertically integrated with a complementary metal oxide semiconductor (CMOS) logic device using through-silicon vias (TSVs) and a unique interposer technology was developed for high-performance, power-efficient, and scalable computing. SMAFTI (SMArt chip connection with FeedThrough Interposer) technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was used for interconnecting the three-dimensionally stacked DRAM and the CMOS logic device . A DRAM-compatible TSV manufacturing process was realized through the use of a “via-first” process and highly doped poly-Si TSVs for vertical traces inside memory dice. A multilayer ultra-thin die stacking process with micro-bump interconnection using a solid-liquid interdiffusion technique was also developed. The thermal aging reliability of the micro-bump interconnection was evaluated by a unique analysis method and its basic reliability was confirmed. Finally, we fabricated a prototype package including stacked DRAM and a CMOS logic device, and observed the combined operation. High-speed 3 Gbit/s signals were successfully transmitted through the fine interposer between the memory and logic.      

Defect-tolerant Logic with Nanoscale Crossbar Circuits

Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect-free crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify reliability thresholds in the ability of defective crossbars to implement boolean logic. These thresholds vary among different implementations of the same logical formula, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components. We illustrate these choices for binary adders. For instance, one adder implementation yields functioning circuits 90% of the time with 30% defective crossbar junctions using an area only 1.8 times larger than the minimum required for a defect-free crossbar. We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.     

量子逻辑电路故障检测定位及自修复方法研究

针对量子逻辑电路规模逐渐增大,电路可靠性逐渐下降的问题,提出基于单个量子逻辑门在线故障检测定位方法,该方法使用新构造的检测信号生成门与故障检测门,利用奇偶保持特性判断待测量子逻辑门是否发生故障,同时在设计过程中对信号检测电路进行检验,保证检测电路的正确性。此外提出了基于硬件冗余的量子逻辑电路自修复设计方法。实验结果表明,文中故障检测方法在量子门和垃圾位等性能指标上相对已有方法均有了改进,首次实现的量子逻辑电路的自修复设计大大提高了电路的容错能力和可靠性。     

Deterministic reliability-modeling of dynamic redundancy

Temporal logic, an extension of the traditional Boolean logic, is applied to deterministic reliability modeling and probabilistic analysis of systems with dynamic redundancy. Temporal logic is introduced, and the temporal structure function is defined. The expressions of temporal logic for active and passive redundancy are explained, followed by a discussion of switches. The concept of the temporal structure function is illustrated by important classes of dynamic systems. It is shown how temporal specifications of structural reliability facilitate subsequent probabilistic analysis and make the reliability analysis of complex dynamic systems feasible     

An overview of logic architectures inside flash memory devices

In the past few years, the complexity of logic functions and architectures inside a flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.     

一种高可靠大容量星载存储器的设计与研究

凭借着存储密度大和存储速率高的特点,基于NANDFlash的大容量存储器在星载存储领域得到了广泛的应用,由于NAND Flash本身存在缺陷,基于NAND Flash的大容量存储器在恶劣环境下的可靠性难以保证.提出了通过FPGA设计SRAM对关键数据三模冗余读取和缓冲、NAND Flash阵列热备份和数据的回放校验以及合理的坏块管理等措施,实现了高可靠性的大容量存储器.实验说明该系统不会因为外在偶然因素而造成数据的不完整,而且整个存储系统的成本开销相对于目前的星载存储器也非常低.     

Flash存储器的冗余实现

Flash存储器是在20世纪80年代末逐渐发展起来的一种新型半导体非挥发性存储器,它具有结构简单、高密度、低成本、高可靠性和系统的电可擦除性等优点,是当今半导体存储器市场中发展最为迅速的一种存储器。文章对Flash存储器的发展现状及发展趋势进行了介绍,分析了Flash存储器的工作机理;并针对Flash存储器是一种数据正确性非理想的器件,在使用中可能会有坏损单元,探讨了Flash存储器冗余技术的种类和实现方法。     

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Nano-scale devices are continuously shrinking, operating at lower voltages and higher frequencies. This makes them more susceptible to environmental perturbations and distinguished by their high dynamic fault rates. Redundancy techniques are widely used to increase the reliability of combinational logic circuits. In this work, soft error reliability is improved by using such techniques, and based on probability of occurrence for combinations at the outputs of circuits. A generalized modular redundancy scheme to enhance the reliability of combinational circuits is proposed. Additionally, several aspects regarding the application of this scheme are explored. This comprises types of redundant modules, complexity of voters and single versus multiple outputs protection. Also, a methodology for applying the generalized modular redundancy scheme is developed. Reliability analysis for various benchmarks from the LGSynth91 suite shows that the proposed methodology can achieve reliability figures higher than that of triple modular redundancy. In general, significant overhead savings are accomplished in addition to that superior reliability.     

基于DWL概念的嵌入式存储器内建自修复方法

嵌入式存储器在SoC技术中逐渐成为主体设计结构,由于存储器存在成品率的问题,所以在存储器中设计了内建自测试和内建自修复的策略来解决,其中主要是:基于冗余行的修复策略、基于冗余列的修复策略和基于冗余字的修复策略,然而,在存储器中采用一维冗余块修复策略需要增加更多的冗余块,如果采用二维冗余块修复虽然提高了修复率,但是使得其稳定性和可靠性降低了,为此改进了一种基于DWL修复概念的策略,使其不仅保持了DWL结构的低功耗、提高了冗余资源的利用率,而且快速访问的特性,从而提高了存储器的故障修复率。     

Microcomputer reliability improvement using triple-modular redundancy

Triple-modular redundancy (TMR) is a classical technique for improving the reliability of digital systems. However, applying TMR to microcomputer systems may not improve overall system reliability because voter circuits may contribute as much to system unreliability as the microprocessors themselves. We examine the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems. With careful application, TMR can improve the mission time of a small system by a factor of 3 or more.     

用于SOC测试的一种有效的BIST方法

为了提高SOC芯片的可测性和可靠性,我们提出了一种SOC测试的BIST技术的实现方案.针对某所自行研制的数字模拟混合信号SOC芯片,我们使用了不同的可测性技术.比如对模拟模块使用改进的BIST方法,对嵌入式存储器使用了MBIST技术.一系列的测试实验数据表明,该BIST方法能有效提高测试覆盖率.