软件无线电中的非整数倍采样率转换研究

针对软件无线电接收机中的非整数倍采样率转换问题,本文首先从实现Ａ／Ｂ倍采样率转换出发,介绍了一种采用先Ｂ倍内插再Ａ倍抽取来实现采样率转换的与之相应的内插滤波器的设计。其次,为实现任意非整数倍采样率转换,本文介绍了一种改进型采样率转换结构,并分析了该方法的转换精度以及降低复杂度的实现方法。     

用于软件无线电中的整数倍采样率转换技术

主要讨论了用于软件无线电中的整数倍采样率转换技术。首先讨论了进行整数倍采样率转换的必要性。然后讨论了用于设计抽取器的关键参数,实现结构及其相应滤波器的设计。文章最后讨论了用于频谱成形和通带衰减补偿的FIR滤波器的必要性和设计方法。     

时变CIC滤波器的FPGA实现方法研究

首先介绍了时变CIC滤波器的原理,然后给出了降低硬件实现复杂性的等效变换方法,同时分析了该采样率转换器的转换精度及参数选取对滤波器性能的影响.最后,通过Quaaus软件仿真和应用实例,验证了该方法的有效性.     

多采样率数字滤波器

过去数字滤波器全是单采样率的系统。近年来提出使用多采样率数字滤波器。多采样率数字滤波器是输出采样率与输入采样率或内部处理采样率不同的一种数字系统。本文对这种滤波器的理论基础、分析方法、实现技术与应用做了系统介绍。文中对修改的 Z 变换与普通 Z 变换的关系、采样区间值用修改的 Z 变换与用采样率转换求法的一致性以及用采样率转换一般分析法与将多采样率数字滤波器作为周期性时变离散滤波器特殊情况分析法的一致性做了推导与阐述。     

基于CIC滤波的重采样技术

采样率变换是一种改变数字信号处理速率的方法,在通信工程中有着非常重要的作用,当系统中有多种通信速率时,可以通过采样率变换使速率归一化,简化设计.基于CIC滤波器的重采样技术根据输入时钟和输出时钟进行处理,无需输入和输出时钟的最小共倍数时钟,具有明显的工程意义.     

通信信号变采样率频域实现方法

提出一种通信信号变采样率的频域实现方法。首先,介绍了解析信号的概念及由实信号转换为解析信号的方法;然后,以2倍升采样为例,通过理论分析证明了变采样率频域实现的可行性;接下来,针对整数倍升采样、整数倍降采样和分数倍变采样三种情况,分别介绍了相应的频域处理方法,并进行了仿真验证;最后,简单分析了算法的优点及适用领域。     

以ⅡR滤波器作补偿的CIC滤波器设计

为解决积分梳状(CIC)滤波器通带失真大和阻带衰减小对其应用的限制,在分析传统CIC滤波器幅频特性的基础上,给出一种用二阶ⅡR滤波器作为补偿滤波器级联CIC滤波器的改进方法。仿真结果表明,它与同级数规模的内插二阶多项式CIC滤波器、锐化CIC滤波器(SCIC)相比,通带和阻带的性能得到较大改善,实现复杂度较低。因此,它适用于对通带、阻带性能和实现复杂度要求较高的多采样率转换系统。     

多速率采样中的CIC滤波器设计与分析

CIC滤波器是常用于多速率采样抽取或内插过程中的高效滤波器,具有结构简单,易于工程实现的特点。以提高采样速率为例,首先介绍了内插理论和CIC滤波器原理,重点给出了CIC滤波器设计方法,并分析了CIC滤波器级联级数和滤波器阶数的选取对通带衰减和旁瓣抑制的影响,仿真结果验证了设计方法的有效性和可行性。     

一种类正余弦CIC滤波器

传统CIC滤波器由于其实现不需要乘法器和存储器,因此已在各种变采样率系统中得到了广泛的应用。但是传统CIC滤波器的通带失真较大,阻带衰减较小,而且其积分器工作在高采样率端,这很大程度限制了它在对性能要求较高的变采样率系统中的应用。而后来提出的各种CIC滤波器,如锐化CIC滤波器、ISOP-CIC滤波器和CIC-Cosine滤波器等,或者只改善通带特性,或者只改善阻带特性,或者积分器运行在高采样率端。本文在分析对比了传统的CIC滤波器、锐化CIC滤波器、ISOP-CIC滤波器和CIC-Cosine滤波器的频率特性的基础上,引入一种类余弦预滤波器和一种类正弦预滤波器,再加上多级级联的传统CIC滤波器,构成一种多级结构的类正余弦CIC滤波器。所引入的类正弦预滤波器和类余弦预滤波器分别用于减小CIC滤波器的通带失真和增大其阻带衰减。仿真结果表明,所提出的类正余弦CIC滤波器比传统的CIC滤波器、ISOP-CIC滤波器、CIC-Cosine滤波器都具有更小的通带失真和更大的阻带衰减。同时所引入的两级预滤波器工作在低采样率端,并且通过使用多相分解技术同样可使多级级联的CIC滤波器工作于低采样率端。      

一种新的带通信号采样方法

本文提出一种新的带通信号采样方法,实现对带通信号的“等效”低通信号采样。带通信号实际采样率仅为输出端所获同相分量和正交分量采样率的两倍,可以直接确定采样频率和设计低通抗混叠滤波器。该采样方法使用滤波器的多相结构实现,这种实现方法特别适合于线性相移FIR滤波器。     

Design of Dual‐Mode Digital Down Converter for WCDMA and cdma2000

We propose an efficient digital IF down converter architecture for dual‐mode WCDMA/cdma2000 based on the concept of software defined radio. Multi‐rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual‐mode receiver for WCDMA and cdma2000. A sub‐sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi‐rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.     

一种可编程的14位CIC内插滤波器

CIC滤波器作为一种高效的多采样器件,具有低通滤波的作用。它仅利用加法器、减法器和寄存器(无需乘法器),实现简单、成本低且速度高,因此被广泛应用。文章介绍了一种2～63倍内插率可编程的14位CIC内插滤波器的结构和特性,讨论了在设计中应注意的溢出保护、CIC通带补偿等问题。     

基于优化混频器的数字下变频系统的设计与实现

在利用频谱分析仪对信号进行实时频谱监测过程中,针对其数字下变频模块精度不高、逻辑资源耗费大、难以对数字中频信号进行实时处理的问题,本文对传统数字下变频系统的混频器模块进行优化并提出一种高效的数字下变频(DDC)系统。首先,设置模数转换器(ADC)的采样率为载波中心频率的4倍且采样率转换比率和子ADC的数量是4的正整数倍,此时混频器可以完全合并到多相CIC抽取滤波器中。接着,基于优化的混频器构建一套DDC系统,并为每个系统节点合理分配采样率转换倍数。最后,加入CIC补偿滤波器,提高数据传输过程中的精度。实验结果表明,与传统DDC相比,优化后的DDC资源消耗减少,数据精度误差从1.7%减小到0.8%。基本满足功耗低、精度高、稳定运行等要求。     

Linear-phase FIR interpolation, decimation, and mth-band filters utilizing the farrow structure

This paper introduces novel linear-phase finite-impulse response (FIR) interpolation, decimation, and Mth-band filters utilizing the Farrow structure. In these new overall filters, each polyphase component (except for one term) is realized using the Farrow structure with a distinct fractional delay. The corresponding interpolation/decimation structures can therefore be implemented using only one set of linear-phase FIR subfilters and one set of multipliers that correspond to the distinct fractional delays. The main advantage of the proposed structures is that they are flexible as to the conversion factors, and this also for an arbitrary set of integer factors, including prime numbers. In particular, they can simultaneously implement several converters at a low cost. The proposed filters can be used to generate both general filters and Mth-band filters for interpolation and decimation by the integer factor M. (In this paper, a general filter for interpolation and decimation by M means a filter having a bandwidth of approximately /spl pi//M without the restriction that /spl pi//M be included in the transition band. This is in contrast to an Mth-band filter whose transition band does include /spl pi//M.) In both cases, the overall filter design problem can be posed as a convex problem, the solution of which is globally optimum. Design examples are included in the paper illustrating the properties and potentials of the proposed filters.     

软件无线电数字变频系统设计与实现

根据软件无线电数字变频的原理,设计和实现了基于软件无线电的数字变频系统.通过System Generator系统设计工具,重点进行了NCO,CIC,HB和FIR滤波器等系统组成部分的建模设计,并没有直接调用System Generator设计工具自带的完整功能模块,其中CIC采用Hogenauer滤波器设计,FIR滤波...     

Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter

In sampling rate conversion between two different formats, the desired output sample values are the interpolated sample values at noninteger (or, integer) multiples of the original sampling period. In this brief, we present an efficient structure for sampling rate conversion from 44.1-kHz compact disc to 48-kHz digital audio tape formats. For efficient conversion, we propose a new infinite-impulse response (IIR) fractional delay filter based on Thiran-based IIR allpass filter. It is shown that the proposed method requires less hardware complexity and maintains high quality of signal-to-noise ratio compared with other methods     

Application of filter sharpening to cascaded integrator-combdecimation filters

A new architecture for the implementation of high-order decimation filters is described. It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filter's passband response. This allows the first-stage CIC decimation filter to be followed by a fixed-coefficient second-stage filter, rather than a programmable filter, thereby achieving a significant hardware reduction over existing approaches. Furthermore, the use of fixed-coefficient filters in place of programmable-coefficient filters improves the overall throughput rate. The resulting architecture is well suited for single-chip VLSI implementation with very high data-sample rates. We discuss an example with specifications suitable for use in a wideband satellite communication subband tuner system and for signal analysis     

Design of selective CIC filter functions

The aim of this letter is to provide graphs which can be used to design a novel class of selective CIC (Cascaded-Integrator–Comb) filters given insertion loss specification. The goal is to choose the free integer filter parameters such that the filter function yields a desired frequency response. To determine the filter parameters needed to satisfy the desired specifications, one can use the graphs of normalized passband and stopband cut-off frequencies versus filter order N. Two graphs, one for maximum attenuation in the passband and one for minimum attenuation in the stopband, are given here. Achieved improvement of performances of the novel class of CIC filter functions over the classical CIC filters is also given. In case of N = 7, the novel class of CIC filter functions gives improvements of 27.68 dB, 47.29 dB and 66.53 dB for different values 1, 2 and 3 of free parameter L, respectively.     

On the use of interpolated second-order polynomials for efficientfilter design in programmable downconversion

Interpolated second-order polynomials (ISOPs) are proposed to design efficient cascaded integrator-comb (CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOPs can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOPs are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified halfband filter (MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for programmable downconverter is a cascade of a CIC filter, an ISOP, MHBFs, and a programmable finite impulse response filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones