基于QC-LDPC码的空间CCD图像NAND闪存存储纠错

为了提高空间CCD相机图像NAND闪存存储可靠性,提出一种基于QC-LDPC码的NAND闪存纠错算法。首先,分析了NAND闪存纠错信道模型;然后,根据闪存特点提出了一种基于QC-LPDC(1056,1024)码的NAND闪存纠错算法,为了加快编码效率提出了校验矩阵构造和高效编码方法,设计的校验阵均是0和1,只有移位和加法运算,非常适合硬件实现;最后,使用地面检测设备对闪存纠错算法进行了试验验证。结果表明,闪存纠错算法能快速稳定、可靠地工作,计算复杂度比较低,算法复杂度仅具为O(N);算法纠错能力高,误码比(BER)为10-6时,本文算法比RS码多0.47dB编码增益;使用65nm CMOS单元库,系统工作频率为250MHz时解码器数据吞吐率达到7.2Gbps;低误码平层,在误比特率为10-8时未出现误码平层。本文的NAND闪存纠错算法满足了空间相机图像存储系统的应用。     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

损伤恢复机制对3D NAND闪存保持特性的影响

在3D NAND闪存的分布式编程擦除循环实验中发现,存储单元的保持特性随着编程擦除循环周期间隔的增加而改善。对实验数据的分析表明,编程擦除循环周期间隔中发生了损伤恢复,且在损伤恢复的两个机制中,氧化层电荷逸出对保持特性的改善起主要作用,而非界面陷阱修复。这说明,氧化层电荷逸出对于3D NAND闪存的保持特性有着重要影响。此外还发现,由于连续的电荷存储层所导致的电荷横向散布,损伤恢复对3D NAND闪存保持特性的影响与存储单元的编程模式有关。综上,损伤恢复机制是影响3D NAND闪存保持特性的一个重要因素,需要在产品的可靠性表征中予以考虑。     

6G移动网络中闪存系统的性能优化方案:比特重映射

第6代移动通信技术(6G)网络所产生的海量数据对数据存储带来了全新挑战,推动着存储技术的迅猛发展。与非门(NAND)闪存存储器具有读写速度快,可靠性高等优点,故在6G网络中具有广泛的应用前景。为了提高NAND闪存的可靠性,针对两种不同位线结构的错误特性,该文分别提出基于全位线结构的等精度重映射方案和基于奇偶位线结构的不等精度的重映射方案。仿真结果表明,两种新型比特重映射方案有效提升了闪存的误码性能。基于此,该文所提重映射技术可被视作6G网络中可靠而高效的存储优化技术。     

MLC闪存的最小和译码算法研究

随着多级单元(Multi-Level Cell,MLC)闪存存储密度的增加,单元间干扰(Cell-toCell Interference,CCI)成为影响NAND闪存可靠性的主要噪声。针对这种情况,在深入分析MLC闪存信道模型和CCI噪声模型的基础上,利用MLC阈值电压的均匀感知策略获取闪存页中每比特的对数似然比(Log-Likelihood Ratio,LLR)信息,提出了一种MLC型NAND闪存的最小和译码算法。仿真结果表明,在MLC闪存信道下,该方法既可保证闪存单元可靠性,又具有较短闪存单元的读取时间,从而实现了译码复杂度和性能间的良好折衷。     

开放式大容量NAND Flash数据存储系统设计与实现

完成了一种基于NAND Flash存储介质的开放武大容量数据存储系统设计,包括硬件系统以及软件系统的设计,并在软件设计中重点提出了应用于NAND闪存的数据管理算法,通过二级地址映射,按块中的脏页数回收脏块和按时间标记转移静态信息实现坏块管理,均匀损耗.该设计能为各种存储器件提供底层的NAND闪存存储系统,使其能方便快速地存储数据而不需要考虑NAND闪存的物理特性.     

NAND闪存错误缓解技术综述

NAND闪存以其高存储密度、高速、低功耗等优点被广泛应用于数据存储。三维堆叠闪存技术的出现和多值存储技术的发展进一步提高了密度,降低了存储成本,同时也带来了更加严重的可靠性问题。闪存主控厂商一直采用更强大的纠错码(ECC),如BCH和LDPC码来对闪存中的数据错误进行纠正。但当NAND闪存中的错误数超出ECC纠错能力时,错误将无法被纠正,因此研究人员提出了多种基于NAND闪存的错误缓解技术作为ECC的补充方案。本文介绍了NAND闪存的工作原理和错误模式,对最新的错误缓解技术进行综述,为设计更加可靠的存储解决方案提供了有益参考。     

赛普拉斯West Bridge控制器适用于PMP、PND、无线网卡及其它嵌入式应用

赛普拉斯半导体公司推出了一款具备多层单元(MLC)NAND闪存支持能力的新型West Bridge外设控制器,可为设计者采用成本最低、密度最高的闪存存储器提供支持.这款West BridgeAstoria?控制器最高支持16个MLC NAND闪存设备,而MLC NAND闪存与相同存储密度的单层单元(SLC)NAND闪存相比,其成本降低了3倍.     

闪存市场新格局

在过去的9个月里,闪存市场可谓翻天覆地的变化.受到消费电子产品持续需求的影响,一直苦苦追赶的NAND闪存终于在2005年第1季度盈利首次超过NOR闪存,此后一直保持优势至今.而就在此前不久,Apple爆料:新型的iPod将采用容量高达1GB的NAND闪存代替HDD.甚至,Apple很快将会采用4GB的NAND闪存代替同样容量的HDD,用于iPod迷你MP3播放器.一时之间,NAND闪存风生水起,而同属闪存一分子的NOR偃旗息鼓,有点风光不再.     

与NAND Flash正面交锋Spansion舞剑意在数据闪存市场

以往NOR闪存与NAND闪存的应用市场可说是泾渭分明,前者多为小容量、代码应用,后者则主要用于大容量数据存储.然而Spansion所推出的ORNAND闪存却极有可能打破这样的界线,因为它同时具备了NOR闪存的高可靠性和快速读写能力以及NAND闪存高容量、低成本特色,大有与NAND在数据闪存市场一争高低的能力.     

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme     

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

A compact on-chip ECC for low cost flash memories

A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10^-4 to 10^-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA     

A quick intelligent page-programming architecture and a shieldedbitline sensing method for 3 V-only NAND flash memory

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-μm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-μs random access time with a 2.7-V power supply. The page-programming is completed after the 40-μs program and 2.8-μs verify read cycle is iterated 4 times. The block-erasing time is 10 ms     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

A dual-page programming scheme for high-speed multigigabit-scaleNAND flash memories

To realize a low-cost and high-speed programming NAND flash memory, a new programming scheme, a “dual-page programming scheme,” has been proposed. This architecture drastically increases the program throughput without circuit area overhead. In the proposed scheme, two memory cells are programmed at the same time using only one page buffer. Therefore, the page size, i.e., the number of memory cells programmed simultaneously, is doubled and the program speed is improved. As the number of page buffers required in the proposed scheme is the same as that in the conventional one, there is no circuit area increase. This novel operation is made possible by using a bitline as a dynamic latch to temporarily store the program data. As a result, the programming is accelerated by 73% in a 1-Gb generation and 62% in a 4-Gb generation, 18.2-MB/s 1-Gb or 30.7-MB/s 4-Gb NAND flash memory can be realized with this new architecture     

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.      

On-chip error correcting techniques for new-generation flash memories

In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.