Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

Surface-charge properties of fluorine-doped lead borosilicate glass

Surface-charge configurations, together with stability under bias-temperature (BT) stress, for F-doped and Na-doped lead borosilicate glass were investigated by using C-V and I- V measurements on metal-glass-silicon capacitors and on diodes passivated with the glass. The C-V characteristics showed an increase in negative charge for F doping and in positive charge for Na doping. Alkali impurities in the glass mainly controlled the surface-charge shift during BT, but additional changes, similar to those for Na doping but reversing the sign of the charge, took place by F doping. The leakage current decrease in the diode passivated with F-doped glass, which contradicts the results of C-V measurement, may be due to the education of the generation current by the interaction between the silicon surface and F^- ions     

Electrical characterization and modeling of alternating-currentthin-film electroluminescent devices

Electrical characterization of evaporated ZnS:Mn alternating-current thin-film electroluminescent (ACTFEL) devices is accomplished by capacitance-voltage (C-V) analysis. Interpretation of these C-V characteristics is aided by SPICE modeling and by electrical characterization of an ideal ACTFEL device constructed from discrete components, based on a simple equivalent circuit for the ACTFEL device. Various features of the C -V curve are ascribed to equivalent circuit parameters and associated device physics parameters     

Modeling and experimental results for C(V) in anabrupt isotype n Al0.5Ga0.5As/GaAs heterojunction

The differential capacitance C of an abrupt isotype n Al_0.5 Ga_0.5As/GaAs heterojunction has been modeled by directly calculating the dependence of the space charge on the voltage V at its terminals. The electron charge distribution was calculated considering the 2-D electron gas by simultaneously solving the Schrodinger and the Poisson equations, DX centers included. Results from this model predict an asymmetric bell-shape dependence of C on V, with a maximum near the contact potential, and are in good agreement with experiment. This further provides experimental evidence of Γ-Γ and X-X valley coupling for electrons traveling across the heterojunction. For voltage values not too close to the contact potential, it was possible to find a simple method, based on a total depletion, that gives a good fit to experiment     

Frequency-dependent capacitance-voltage characteristics foramorphous silicon-based metal-insulator-semiconductor structures

A frequency-dependent capacitance-voltage model for the a-Si:H-based MIS structure is presented along with an alternative direct measurement method. The static C-V model is derived based on the static I-V model developed using the simplified CFO band model for the a-Si bulk bandgap states and the simplified Davis-Mott model for the surface states. The frequency variation of the measured capacitance, using a somewhat modified TFT, is modeled with the lateral flow transmission line model. These models can be used to monitor TFT-fabrication parameters and to extract accurate capacitance model parameters of TFTs     

Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

Counting the number of minimum cuts in undirected multigraphs

The problem of counting the number of cuts with the minimum cardinality in an undirected multigraph arises in various applications, such as testing the super-λ-ness of a graph, as described by F.T. Boesch (1986), and calculating upper and lower bounds on the probabilistic connectedness of a stochastic graph G in which edges are subject to failure. It is shown that the number |C( G)| of cuts with the minimum cardinality λ(G) in a multiple graph G=(V,E) can be computed in O(|E|+λ(G)|V|² +λ(G)|C(G)||V|) time     

On the charge control of the two-dimensional electron gas foranalytic modeling of HEMTs

A simple charge control model is developed for the two-dimensional electron gas (2-DEG) of high-electron-mobility transistors (HEMTs). This model explicitly takes into account the effective distance of the 2-DEG from the heterointerface and has been developed for use in analytic I-V and C-V modeling. In this model, the Fermi energy level versus the 2-DEG sheet carrier-concentration is represented by a simplified expression derived from the triangular potential well approximation and is shown to be dominated by terms with different functional forms in two distinct operation regions: a moderate carrier-concentration region and a subthreshold region. The validity of the analytic charge control model is supported by the calculated results of a self-consistent quantum mechanical model     

Measurements and modeling of the n-channel MOSFET inversion layermobility and device characteristics in the temperature range 60-300 K

Discussed is the use of the high-frequency split C-V method to measure accurately the effective mobility of the n-channel MOS transistor as a function of temperature, bulk charge Q _b, and inversion layer charge Q_i. The experimental data for Q_b and Q_i were verified by comparison with the results of numerical simulation. The results of the measurements were used to develop the mobility model, which is accurate in the 60-300 K temperature range. The proposed mobility model incorporates Coulombic, lattice, and surface roughness scattering modes and generalizes the previous model, which was limited to low-temperature operation of the MOSFET. The deviation from the universal (for different back biases) μ(E_eff) dependence, which becomes more pronounced at low temperatures and low E_eff, is included in the model and can be associated with the Coulomb scattering mechanism. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics for different temperatures     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

MOSFET capacitance and conductance in the saturation regime

The relationship between capacitance and conductance of a MOSFET is examined in the region where velocity saturation dominates. In this domain it is shown that charge on the drain terminal (physically distinct from that in the channel) most be considered in order to keep the model from predicting the unphysical result that C_gd is negative. It is also shown that, under the same assumptions, g_m<C_gg/τ where g _m is the transconductance, τ is the transit time, and C_gg is the gate capacitance     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

A new method for fixed oxide charge determination using a dual-gateMOS capacitor

A new method for fixed oxide charge determination at the silicon-silicon-dioxide interface is presented. It is based on high-frequency C-V measurements of a dual-gate MOS capacitor. Using this technique the fixed oxide charge can be accurately without knowledge of the work-function difference by means of one simple measurement. Due to its simplicity and ease of automation it can be applied to characterization and process optimization of MOS technology     

Low-temperature mobility measurements on CMOS devices

The surface channel mobility of carriers in n- and p-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 K. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP) which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appeared to have different temperature dependences for n- and p-channel devices. The electron mobility increased with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibited a different temperature behavior depending upon whether the gate voltage corresponded to strong inversion or was near threshold     

MOS flat-band capacitance method at low temperatures

The expression C_FB=C_ox×(ϵ_si /L_D)/[C_ox+(ϵ_si /L_D)] (where L_D is the Debye length), commonly used for the flatband capacitance of the MOS structure, is invalid in the temperature range below 100 K. Consequently, significant error may be encountered when the flatband capacitance method is used to extract the flatband voltage, V _FB, which is of considerable interest for both the modeling and characterization of MOS devices. To extend this method to low-temperature CMOS applications one has to use a more general model that can be obtained by applying Fermi-Dirac statistics and taking into account the impurity freeze-out effect. It is shown that when the temperature dependence of V_FB is extracted using this approach, the experimental data for n⁺ polysilicon gate MOS capacitors are in good agreement with a simple method     

Leakage-current-induced hot-carrier degradation of p-channelMOSFETs

Leakage-current-induced hot-carrier effects have been observed during stressing of p-channel MOSFETs in the OFF state with V _GS>0 V and V_DS<0 V. This mode of stressing results in increased leakage current and a positive shift in the value of V_GS, corresponding to the onset of avalanche breakdown of the drain junction. These effects are related to generation of interface states near the drain in forward-mode operation. By comparison, conventional stressing in the ON state with V _GS<0 V and V_DS<0 V resulted in little change in these p-channel MOSFET characteristics     

A new technique for determining the generation lifetime profile inthin semiconductor films with application to silicon-on-insulator (SOI)substrates

A differential technique which uses reverse-biased current-voltage (I-V) and capacitance-voltage (C-V) measurements on a p-n junction or a Schottky barrier diode for determining the generation lifetime profile in thin semiconductor films is discussed. It is shown that the bias-independent current can be eliminated by this differential technique. Furthermore, any error caused by field-enhanced current can be estimated. This method has been used to determine the generation lifetime profile in thin silicon epitaxial film grown on SIMOX substrates     

Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Electrical transport properties of crystalline siliconcarbide/silicon heterojunctions

The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I-V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV_bi/kT ) exp(V/ηkT), where V_bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×10²¹ cm ^-3 and 0.78m₀, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs)