IPv4/IPv6双栈四分搜索路由查找算法与实现

IPv4／IPv6双协议栈核心路由器需要高性能一体化路由查找。传统的前缀长度二分查找算法完成一次IPv6路由查找需多达7步搜索，而核心路由器常用的单级TCAM方案要求转发表的存储必须按前缀长度相对地址降序排列，这种降序操作严重影响表项更新速度和路由查找连续性。与对前缀长度二分查找和单级TCAM方案不同，作者提出了一种独特的对前缀范围四分搜索路由查找算法，并用3级TCAM实现了IPv4／IPv6双栈一体化QSPE查找方案。一次查找仅需3步搜索、转发表无需排序、表项更新快、查找速率高且连续性好，满足IPv4／IPv6双栈核心路由器OC-768（40Gbit/s）端口的线速率转发。     

快速路由查找算法的研究

首先给出了现有的路由查找算法以及这些算法的优缺点,在此基础上提出了基于二分查找Trie的路由查找算法.另外,文章给出了算法在IPv6T 实现方案.该算法具有查找、更新速度快的特点,由于算法简单,容易实现,因此具有较高的实用价值.     

基于并行BP神经网络的路由查找算法

结合Bloom-filter算法和并行反向传播神经网络,提出了一种新的基于并行神经网络的路由查找算法(BFBP)。该算法满足路由查找的需求,只需学习路由条目的网络ID,且易于扩展到IPv6地址查询。研究结果表明,相比于己有的神经网络路由查找方法,该算法需要学习的条目数平均减少了520倍,提高了学习效率,为神经网络应用于路由查找创造了有利条件。     

基于前缀区间集合的IPv6路由查找算法

对IPv6相关的通用型与特定型路由算法进行了分析,重点研究了以BSR为基础的IPv6路由算法在查找和更新时的不平衡问题,提出了基于前缀区间集合的IPv6路由算法。通过对路由前缀（N）进行范围（K）、集合（M）划分以及更新节点自修复提高查询速度、降低不平衡性的影响,具有O(log2N/K)和O(log2N/K+2M)的查询与更新时间复杂度,空间复杂度为O(K+2N)。实验表明,该算法具有良好的查询性能,降低了更新不平衡性的影响。     

TSB:一种多阶段IPv6路由表查找算法

充分分析IPv6地址结构、IPv6地址分配策略和IPv6骨干网路由表的特点后,将二叉树、段表和路由桶技术相结合,提出一种多阶段IPv6路由表查找算法.和已有算法相比,提出的算法查找速度快、占用内存少、扩展性好、支持增量更新.实验结果表明算法的软件参考实现在装有P4 2.4GHz CPU,512M DDR333 内存和Linux 操作系统的普通PC 机上的查找能力可以到达16MPPS(Million Packet per Second),这可以满足10Gbps 80 字节IPv6最小包的线速转发.对于当前IPv6骨干网BGP 路由表,算法的参考实现只占用几百K 字节的内存.     

多分枝trie树路由查找算法研究

为了解决路由器报文转发中路由查找速度慢的瓶颈问题,在分析了路由器中广泛使用的各种典型IP 路由算法的基础上,提出一种基于多分枝trie树的改进路由查找算法.在多分枝trie树中取消前缀查找,组成一个大的中间结点.在中间结点之间采用多分支步长查询,中间结点的内部使用二进制trie树来表示.仿真结果表明,改进的多分支trie树具有访存次数少,查询速度快,占用存储空间少,更新开销小等特点,并且对IPv4和IPv6地址都可以适用.     

基于分割多分枝Trie树的并行路由查找算法

为解决在多核处理器平台下路由器报文转发时路由查找速度慢的“瓶颈”问题,提出了一种基于分割的多分枝 Trie树的并行路由查找算法。该算法将一棵多分枝 Trie 树根据处理器的核数分割成若干子树,每棵子树又构成一棵单独的多分枝Trie树,子树中取消了前缀查找,采取组成一个大中间节点的方式,在中间节点之间采用固定步长查询,中间节点内部采用二进制Trie树来表示。实验结果表明,该算法具有访存次数少、查询速度快、占用存储空间少和更新开销小等特点,同时适用于IPv4和 IPv6地址。     

多分枝trie树路由查找算法研究

为了解决路由器报文转发中路由查找速度慢的瓶颈问题,在分析了路由器中广泛使用的各种典型IP路由算法的基础上．提出一种基于多分枝trie树的改进路由查找算法。在多分枝trie树中取消前缀查找,组成一个大的中间结点。在中间结点之间采用多分支步长查询,中间结点的内部使用二进制trie树来表示。仿真结果表明,改进的多分支trie树具有访存次数少,查询速度快,占用存储空间少,更新开销小等特点,并且对IPv4和IPv6地址都可以适用。     

基于非重叠前缀集合的并行路由查找系统

快速的路由查找机制是高性能路由器设计的关键.最长匹配查找是路由查找的难点所在.本文提出一个并行路由查找系统.它使用一种路由表划分方法,可将路由表中的前缀划分为若干个集合,集合内前缀没有重叠.从而把路由表前缀的最长匹配查找转化为若干个集合内前缀的唯一匹配查找.基于这种方法,本文还提出一个通用的并行路由查找框架,框架适用于大多数路由查找算法.并行查找框架可简化查找算法的设计,提高查找算法的速度.使用二分查找算法,并行查找系统可以达到log₂(2N/B)的查找复杂度 (N为路由表前缀数目,B为大于4的整数).同时,并行查找系统对IPv6也具有很好的扩展性.     

一种基于Trie的快速IP路由查找算法

Internet的飞速发展要求核心路由器能够实现快速的分组转发和路由更新功能,实现这一功能的关键是路由表的组织结构和快速的路由查找算法.提出了带有转发域信息树的多分支Trie结构路由查找算法,它由固定步长的多分支Tile结构的路由表和转发域信息树两部分组成.对于一个长度为w的路由前缀,其查找、插入、删除路由的时间复杂度均为O((w-m)/n+1),其中m、n为Trie树的步长.它解决路由查找过程中快速更新的问题,具有算法简单、查找速度快、易于更新、空间利用率高、便于向IPv6过渡等优点.     

Longest prefix matching using bloom filters

We introduce the first algorithm that we are aware of to employ Bloom filters for longest prefix matching (LPM). The algorithm performs parallel queries on Bloom filters, an efficient data structure for membership queries, in order to determine address prefix membership in sets of prefixes sorted by prefix length. We show that use of this algorithm for Internet Protocol (IP) routing lookups results in a search engine providing better performance and scalability than TCAM-based approaches. The key feature of our technique is that the performance, as determined by the number of dependent memory accesses per lookup, can be held constant for longer address lengths or additional unique address prefix lengths in the forwarding table given that memory resources scale linearly with the number of prefixes in the forwarding table. Our approach is equally attractive for Internet Protocol Version 6 (IPv6) which uses 128-bit destination addresses, four times longer than IPv4. We present a basic version of our approach along with optimizations leveraging previous advances in LPM algorithms. We also report results of performance simulations of our system using snapshots of IPv4 BGP tables and extend the results to IPv6. Using less than 2 Mb of embedded RAM and a commodity SRAM device, our technique achieves average performance of one hash probe per lookup and a worst case of two hash probes and one array access per lookup.     

Scalable, Memory Efficient, High-Speed IP Lookup Algorithms

One of the central issues in router performance is IP address lookup based on longest prefix matching. IP address lookup algorithms can be evaluated on a number of metrics—lookup time, update time, memory usage, and to a less important extent, the time to construct the data structure used to support lookups and updates. Many of the existing methods are geared toward optimizing a specific metric, and do not scale well with the ever expanding routing tables and the forthcoming IPv6 where the IP addresses are 128 bits long. In contrast, our effort is directed at simultaneously optimizing multiple metrics and provide solutions that scale to IPv6, with its longer addresses and much larger routing tables. In this paper, we present two IP address lookup schemes—Elevator-Stairs algorithm and logW-Elevators algorithm. For a routing table with$N$prefixes, The Elevator-Stairs algorithm uses optimal$cal O(N)$memory, and achieves better lookup and update times than other methods with similar memory requirements. The logW-Elevators algorithm gives$cal O(log W)$lookup time, where$W$is the length of an IP address, while improving upon update time and memory usage. Experimental results using the MAE-West router with 29 487 prefixes show that the Elevator-Stairs algorithm gives an average throughput of 15.7 Million lookups per second (Mlps) using 459KB of memory, and the logW-Elevators algorithm gives an average throughput of 21.41Mlps with a memory usage of 1259KB.     

H‐LCFST: a hash lowest cost first search tree for flexible packet classification

Packet classification (PC) categorizes incoming packets into multiple forwarding classes in a router based on predefined filters. It is one of the most important enabling technologies for next generation network services, for example, firewall, quality of service routing, load balancing, and virtual private network. IPv6 technology has posed a great challenge on the wire‐speed router for the PC because of its longer IP addresses. In this paper, we propose a new algorithm to support both IPv4 and IPv6, called hash lowest cost first search tree (H‐LCFST) for the PC. The H‐LCFST combines the advantages of the hash tree and a novel LCFST to achieve a better lookup performance. More important, the H‐LCFST algorithm is able to utilize the features of distinct IPv4 and IPv6 classifiers and design corresponding data structure for different characteristics of the classifiers, with which it is able to avoid the performance degrade because of the longer address of the IPv6. The experiment results show that our proposed algorithm has only approximately seven times of memory accesses for the IPv4/IPv6 PC, which make it to be the fastest PC solutions so far. Moreover, it occupies extremely small memory and supports incremental update at the same time. Copyright © 2016 John Wiley & Sons, Ltd.     

On a trie partitioning algorithm for power-efficient TCAMs

Internet routers conduct routing table (RT) lookup based on the destination IP address of the incoming packet to decide which output port to forward the packet. Ternary content-addressible memories (TCAM) uses parallelism to achieve lookup in a single cycle. One of the major drawbacks of TCAM is its high-power consumption. Trie-based architecture has been proposed to reduce TCAM power consumption. The idea is to use an index TCAM to select one of many data TCAM blocks for lookup. However, power reduction is limited by the size of the index TCAM, which is always enabled for search. In this paper we develop a simple but effective trie-partitioning algorithm to reduce the index TCAM size, which achieves better reduction in power consumption, and at the same time guarantees full TCAM space utilization. We compared our algorithm (LogSplit) with PostOrderSplit (IEEE INFOCOM, 2003). For two real-world RTs (AADS and PAIX), the size of the index TCAM generated by LogSplit is 55–70% of that generated by PostOrderSplit; the largest power reduction factor of LogSplit is 41 for AADS and 68 for PAIX, while the largest power reduction factor of PostOrderSplit is 33 for AADS and 52 for PAIX. The improvement is even more significant in the worst case: the size of the index TCAM generated by LogSplit is 18–30% of that generated by PostOrderSplit for IPv4, and less than 1% of that generated by PostOrderSplit for IPv6; the largest power reduction factor of LogSplit is 173 for both IPv4 and IPv6, while the largest power reduction factor of PostOrderSplit is only 82 for IPv4 and 41 for IPv6. Copyright © 2007 John Wiley & Sons, Ltd.     

IP lookups using multiway and multicolumn search

IP address lookup is becoming critical because of increasing routing table sizes, speed, and traffic in the Internet. Given a set S of prefixes and an IP address D, the IP address lookup problem is to find the longest matching prefix of D in set S. This paper shows how binary search can be adapted for solving the best-matching prefix problem. Next, we show how to improve the performance of any best-matching prefix scheme using an initial array indexed by the first X bits of the address. We then describe how to take advantage of cache line size to do a multiway search with six-way branching. Finally, we show how to extend the binary search solution and the multiway search solution for IPv6. For a database of N prefixes with address length W, naive binary search would take O(W*log N); we show how to reduce this to O(W+log N) using multiple-column binary search. Measurements using a practical (Mae-East) database of 38000 entries yield a worst-case lookup time of 490 ns, five times faster than the Patricia trie scheme used in BSD UNIX. Our scheme is attractive for IPv6 because of its small storage requirement (2N nodes) and speed (estimated worst case of 7 cache line reads per lookup)     

High-speed IP routing with binary decision diagrams based hardware address lookup engine

With a rapid increase in the data transmission link rates and an immense continuous growth in the Internet traffic, the demand for routers that perform Internet protocol packet forwarding at high speed and throughput is ever increasing. The key issue in the router performance is the IP address lookup mechanism based on the longest prefix matching scheme. Earlier work on fast Internet protocol version 4 (IPv4) routing table lookup includes, software mechanisms based on tree traversal or binary search methods, and hardware schemes based on content addressable memory (CAM), memory lookups and the CPU caching. These schemes depend on the memory access technology which limits their performance. The paper presents a binary decision diagrams (BDDs) based optimized combinational logic for an efficient implementation of a fast address lookup scheme in reconfigurable hardware. The results show that the BDD hardware engine gives a throughput of up to 175.7 million lookups per second (Ml/s) for a large AADS routing table with 33 796 prefixes, a throughput of up to 168.6 Ml/s for an MAE-West routing table with 29 487 prefixes, and a throughput of up to 229.3 Ml/s for the Pacbell routing table with 6822 prefixes. Besides the performance of the scheme, routing table update and the scalability to Internet protocol version 6 (IPv6) issues are discussed.