基于可拓学及模糊聚类分析的空气污染预测

为预测未来几年某地区的空气质量,提出了一种基于可拓学的模糊聚类方法.该方法利用污染指数和某地区历年三大产业产值以及人口总数构造经典域和节域物元,应用物元和可拓集合中的关联函数建立预测模型,利用样本之间的模糊关系分析样本之间的关联程度,将精确的数学方法和模糊概念结合起来,给出了模糊聚类分析对各年空气污染物样本进行分类的步骤.     

基于采样的大规模图聚类分析算法

针对当前聚类方法（例如经典的GN算法）计算复杂度过高、难以适用于大规模图的聚类问题，本文首先对大规模图的采样算法展开研究，提出了能够有效保持原始图聚类结构的图采样算法（Clustering-structure Representative Sampling，CRS），它能在采样图中产生高质量的聚类代表点，并根据相应的扩张准则进行采样扩张.此采样算法能够很好地保持原始图的内在聚类结构.其次，提出快速的整体样本聚类推断（Population Clustering Inference，PCI）算法，它利用采样子图的聚类标签对整体图的聚类结构进行推断.实验结果表明本文算法对大规模图数据具有较高的聚类质量和处理效率，能够很好地完成大规模图的聚类任务.     

汉语文本聚类及其算法设计

主要针对传统的聚类算法倾向于识别大小类似的球形聚类簇，且对离群数据较为敏感等问题，利用聚类簇代表点选取的方法，同时结合基于人进行聚类判断所遵循的基本原则，即聚类中对象间距离应小于聚类间距离，设计了一种有效的聚类算法，实验结果表明算法是有效的。     

可拓知识空间和可拓知识网格模型(Ⅰ):可拓知识空间

本文提出了可拓知识空间概念，建立相应的可拓知识空间相关操作，并在此基础上进一步构架可拓知识空间语义网和可拓知识网格模型。本文第一部分论述了上述模型的建立过程，提出了可拓知识空间关联函数计算方法，第二部分分析了可拓知识空间操作在可拓知识空间语义网上的对应行为，并讨论了可拓知识网格服务。上述方法和模型对于大规模可拓问题求解与计算具有一定意义。     

基于Spark并行化的改进K-means轨迹聚类的方法

<正>本文设计了一种对K-means初始化改进的Canopy+Kmeans++聚类方法，提高上轨迹聚类算法的效率，为进一步提升轨迹大数据聚类的迭代计算效率，本文利用Spark计算架构的可伸缩性和分布式等特，实现Canopy+Kmeans++轨迹聚类算法的并行化，并通过对比实验来证明该并行化聚类方案的有效性。     

一种基于Web文本聚类的用户兴趣发现模型的研究

研究了一种基于Web文本聚类的用户兴趣发现方法．他通过Web文档信息获取，文本的形式表示，以及Web文本聚类方法最终提取用户兴趣知识，并给出了一个设计模型。     

可拓知识空间和可拓知识网格模型(Ⅱ):可拓知识网格

第1部分中已介绍了可拓知识空间定义和相关操作，以及可拓知识空间关联函数计算方法。这一部分进一步建立可拓知识空间语义网、可拓知识网格和可拓知识网格服务，并给出实例和相关的分析讨论。     

基于MapReduce的改进k-means文本聚类算法

针对传统k-means文本聚类算法在处理大规模文本数据时扩展性不足的问题,提出了基于MapReduce编程模型的并行k-means文本聚类算法。通过删除离群点和采用高效的初始质心选择策略提高k-means聚类效果,并设计基于MapReduce框架的大规模文本并行聚类模型提高算法的可扩展性。实验证明,该算法在大规模文本聚类中具有良好的聚类效果和可扩展性。     

基于流形聚类的非球类目标多站三维点云配准方法

非球类物体形状结构复杂，利用点云直接进行配准易出现误匹配现象。针对该问题，引入流形上的测地距离结合物体的实际几何形状，将三维点云配准问题转换为聚类问题，提出一种基于流形聚类的多站点云配准方法。首先，将经粗配准后的三维点云划分为若干个聚类；然后，以测地距离作为聚类划分的依据更新聚类中心，同时更新刚性变换，再循环迭代此过程以获得最终配准结果；最后，由于在配准过程中计算测地距离矩阵时易产生计算消耗，引入热梯度法将点集在空间中的遍历过程转换为泊松方程的求解过程以提升效率，完成多站点云配准。在斯坦福大学公共数据集中的Bunny、Dragon等点云数据上的实验结果表明，所提方法可有效将非球类物体的配准精度整体提升20%～30%。     

基于深度学习的知识空间自增扩展方法研究

为解决传统知识空间可拓方法可拓范围小、精度低等问题，文中提出一种基于深度学习算法的知识空间可拓方法。通过将深度学习算法与多模态信息融合方法相结合，构建知识空间扩展框架，包括对现有知识空间的融合与扩展。在空间结构拓展方面，将框架设置为空间组织知识、知识索引、知识导航、知识检索等部分，根据知识序列信息的连续分类实现知识划分。在扩展空间中，通过语义描述技术整合知识元素的多结构状态，实现知识空间的自增扩展。实验结果表明，基于深度学习算法的知识空间扩展方法整体效果较好。     

Evaluating layout area tradeoffs for high level applications

The authors address the problem of evaluating area tradeoffs for VLSI layouts from high-level specifications (typically register-transfer level). An area prediction approach based on two models, analytical and constructive, are presented. A circuit design is partitioned recursively down to a level specified by the user, thus generating a slicing tree. An analytical model is then used to predict the shape function of each of the leaf subcircuits. By traversing the tree in post-order, the shape function of the entire layout design can be predicted constructively. This approach also permits the user to trade off the accuracy of the prediction versus the runtime of the predictor. Such a scheme is quite useful for high level design tasks. The authors show experimentally that the estimates obtained using this model are within 5% of the actual layout area for designs ranging from 125 to 12000 cells     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

Lossless Compression Algorithms for Hierarchical IC Layout

An important step in today's integrated circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. In this paper, we propose two techniques for compressing layout data, including OPC layout, while remaining compliant with existing industry standard formats such as OASIS and GDSII. Our approach is to eliminate redundancies in the representation of the geometrical data by finding repeating groups of geometries between multiple cells and within a cell. We refer to the former as ldquointercell subcell detection (InterSCD)rdquo and the latter as ldquointracell subcell detection (IntraSCD).rdquo We show both problems to be nondeterministic polynomial time hard (NP-hard), and propose two sets of heuristics to solve them. For OPC layout data, we also propose a fast compression method based on IntraSCD which utilizes the hierarchical information in the pre-OPC layout data. We show that the IntraSCD approach can also be effective in reconstructing hierarchy from flattened layout data. We demonstrate the results of our proposed algorithms on actual IC layouts for 90-nm, 130-nm, and 180-nm feature size circuit designs.     

Design of Schottky-barrier diode clamped transistor layouts

Describes an approach to the design of Schottky-clamped integrated circuit transistor layouts. Three-dimensional distributed resistances are modeled using a grid of lumped resistors. A computer circuit analysis program is used to obtain a simple lumped equivalent circuit for the clamped transistor. The equivalent circuit enables accurate prediction of the useful range of d.c. operating conditions for a given structure. An improved small-area clamped transistor layout has been developed using this approach.     

An analysis of the effects of cable layout on cable to antennacoupling inside a screened room

An equivalent circuit model is presented for a screened room emission measurement setup. Transfer functions that are used to illustrate the variations in received emission levels produced by changes in interconnecting cable layout when the cable is placed over a conducting bench in the room are developed. The model is based on a coupled transmission line approach and is valid at frequencies up to 50 MHz     

Quantitative analysis of intermodulation product interference

An analytical technique for estimating the absolute signal strength of externally generated intermodulation (IM) product interference is given. The modeling approach detailed is intended to augment previously published work by providing greater insight into the mechanisms generating IM product interference and may find direct application for siting situations in which equipment parameters and layout are well defined. The layout for a simplified model used to determine externally generated IM product levels is shown; a transmitting antenna illuminates a dipole antenna terminated in a nonlinearity, which reradiates IM product interference that is coupled into the receiving antenna. Actual signal levels are calculated for a canonic case involving a parasitic, center-fed dipole terminated in a nonlinear diode-type junction. The results can be applied readily to any nonlinear function and radiating system     

支持向量机回归法在天线设计中的应用

提出了一种利用支持向量机回归进行天线设计的方法.以印刷偶极子天线为例,通过对3个主要的天线参数进行训练以捕捉天线结构尺寸和天线性能之间的关系,从而建立支持向量机回归模型.该模型在保证快速计算的前提下显示出比神经网络模型更高的计算精度,从而节省天线设计和优化时间.     

GAL: A global-attributes assisted labeling system for outdoor scenes

An approach that extracts global attributes from outdoor images to facilitate geometric layout labeling is investigated in this work. The proposed Global-attributes Assisted Labeling (GAL) system exploits both local features and global attributes. First, by following a classical method, we use local features to provide initial labels for all super-pixels. Then, we develop a set of techniques to extract global attributes from 2D outdoor images. They include sky lines, ground lines, vanishing lines, etc. Finally, we propose the GAL system that integrates global attributes in the conditional random field (CRF) framework to improve initial labels so as to offer a more robust labeling result. The performance of the proposed GAL system is demonstrated and benchmarked with several state-of-the-art algorithms against a popular outdoor scene layout dataset.     

基于拓扑分析的多层通道布线算法

本文提出了一种基于拓扑分析的多层通道布线算法。算法把整个布线过程分成拓扑分层和物理布线两个部分。拓扑分层利用线段交叠图及模拟退火算法解决线段分层及通孔最少化问题，物理布线过程引入虚拟走线道解决交叉问题，再利用轮廓线跟踪的方法来决定最终确定各线段的布线位置。算法还解决了多层布线分层的管脚约束问题和相邻约束问题。实验结果表明，这是一种有效的方法。     

Cell-based layout techniques supporting gate-level voltage scalingfor low power

Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous research focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this correspondence, we present cell-based layout techniques that make the approach feasible. We first propose a new block layout style and a placement strategy to support the voltage scaling with conventional standard cell libraries. Then, we propose a new cell layout style with built-in multiple supply rails so that gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques maintain good power benefit while introducing moderate layout overhead