点云隐式曲面快速重建算法研究

提出一种点云数据隐式曲面高效重建算法。该算法首先基于传统径向基函数隐式曲面重建算法对点云数据进行低解析度、低精度快速插值,然后采用三线性插值对点云数据进行高解析度、低精度插值,最后根据欧氏距离确定点云零水平集附近需要处理的区域,处理过程中只对区域内点云数据进行滤波降噪。与传统方法相比,本文算法既可以保证曲面重建精度,又可以缩短计算时间。在头部点云数据的曲面重建过程中,本文算法能够实现与传统算法相近的精度,同时使插值运算时间减少63.21%。     

兼容多标准的高效运动补偿新结构

为有效解决运动补偿的多标准兼容问题,该文提出了一种改进的适用于多标准运动补偿的新插值算法结构,新插值算法基于文中提出的RL(Rounding Last)策略和DTS(Diagonal Two Step)策略,其采用一种统一的两步插值结构有效地兼容了各标准中亮度分量和色度分量的插值。基于新算法,设计实现了一种可重构的多标准运动补偿硬件电路,该电路采用了基于可变块大小的运动补偿结构。实现结果表明,与JM8.4中基于44固定块大小的运动补偿结构相比,所设计的电路使得带宽需求降低了27%~50%,平均单次访问外部存储器的突发长度提高了1.22~2.25倍;电路在125 MHz工作频率下可满足全高清1080 p (19201080) 30帧/s的实时解码需求。     

多波束回波信号可变带宽滤波算法及其FPGA实现

噪声是限制多波束测深声呐深度估计精度的重要因素,目前在声呐系统中广泛采用的噪声抑制方法是固定带宽滤波。针对测量扇面内不同方向上噪声影响程度不同的特点,该文提出一种新的可变带宽滤波算法并依据多波束回波特性设计了相应的滤波器,与传统滤波方法相比,可以有效地提高信噪比,并且运算量小;其滤波算法结构非常有利于 FPGA的快速实现。文中给出了该滤波算法的FPGA实现结构,并仿真验证了该滤波算法的工程可行性。对湖上试验数据的处理结果验证了该算法的有效性。     

H.264中1/4精度像素插值算法的一种硬件实现架构

提出了一种适用于H.264标准中1/4精度像素插值算法的硬件实现架构.对于亮度分量,采用了一维处理单元(PE)阵列来实现1/4精度像素插值算法中的亮度半像素的插值,同时采用一个6×4的寄存器阵列转置已得到的半像素以进行下一步的亮度的1/4精度像素插值.而对于色度分量,笔者采用了一种只含移位和加法运算的插值核架构来实现色度的1/8像素插值.笔者提出的架构可在一定的时钟周期内,计算出不同位置上的插值像素,且有面积小,速度快的特点.     

基于Cache的HEVC运动补偿带宽优化设计

作为计算量最多的模块之一,运动补偿占用了解码器与片外数据存储器之间约70%的带宽,是实现超高清视频解码的瓶颈。通过所设计的基于Cache的HEVC运动补偿模块,在保证实时解码数据吞吐量的同时,有效减少了80%的带宽消耗。首先,利用由可复用滤波器构成的插值计算模块和2D Cache设计了可并行化流水线数据处理的运动补偿模块,满足计算过程中高数据吞吐量需求。其次,设计高效内部存储器RAM结构,并提出片内Cache功耗降低的有效解决方案。最后,利用了参考帧数据相关性,设计插值顺序重排,将Cache的硬件开销减少了87.5%。基于HM9.0的HEVC标准测试视频序列实验结构表明,该设计显著地减少了带宽消耗和硬件开销。     

H．264／AVC编码器中分数像素的插值算法优化

文中基于H．264/AVC视频编码器的系统芯片设计,对分数像素运动估计(FME)的亮度像素插值算法进行了简化调整;使用JM7．3参考代码模拟了不同分数像素插值算法对编码器性能的影响,通过分析这些插值算法的编码效率和芯片上的实现代价,提出了可以有效节约硬件实现代价的分数像素插值算法。试验结果表明优化后的插值算法可以使分数像素插值结构的硬件实现代价降低30%以上,而平均编码峰值信噪比(PSNR)和压缩率只有很小的损失。     

粒子群算法在三维微带阵列优化设计中的应用

采用粒子群算法与微波仿真软件CST联合仿真的方法,针对拓展吸波带宽或降低吸波材料厚度的不同要求,通过设计不同的适应度函数,实现了对三维微带线阵列吸波结构材料的优化设计。设计结果表明,经过优化设计,吸波材料的吸波带宽可以增加30%,或在吸波性基本不变的条件下材料厚度减少15%。调节适应度函数中的权重,还可以有针对性地拓展吸波材料的频率低频段或高频段。所采用的计算流程可以全程自动进行优化处理。     

基于FPGA的高速定点FFT算法的实现

针对高速实时信号处理的要求,提出一种基于现场可编程门阵列(FPGA)实现64点高速定点快速傅里叶变换(FFT)算法的方法.该方法从运算速度和实现复杂度两方面综合考虑,采用基于按时间抽取的Radix-4算法的三级流水线结构,每级将乘法器的旋转因子输入端固定为常数值,而不是作为变量从ROM中读取,从而减少ROM的读取时间.另外,为了避免溢出,还采用块浮点结构表示数据,节省了大量的硬件资源.从实验结果看,可以满足对数据高速实时处理的要求.     

基于FPGA的红外图像二阶牛顿插值算法的实现

近年来牛顿插值公式被广泛应用于图像插值领域,但是简单的使用牛顿插值公式会造成大量的数据溢出;使用外部存储器进行数据缓冲,占用大量存储资源,使得实时图像延迟一帧.针对以上不足之处设计了一种新的二阶牛顿插值算法在FPGA中的实现方法,首先将牛顿插值公式进行改进,抑制了数据溢出;同时利用FPGA内部逻辑实现数据缓存,在几行时间之内完成数据插值,大大缩短了延迟时间.经实际应用,证明该算法可有效改善边缘模糊和锯齿效应,提高图像质量;同时节省了资源,提高实时性.     

距离徙动校正和斜地变换的实时算法研究

距离徙动校正插值处理是距离多普勒域(RD)算法的重要步骤,图像校正中的斜地变换也需要插值处理,插值处理会对图像引入插值误差。该文分析了距离徙动校正和斜地变换的原理,推导出一种把两种处理结合实现的方法,该方法通过一次插值处理完成距离徙动校正和斜地变换。与传统的实现方法相比,该方法减少了图像中由于插值处理引入的误差,提高了图像处理的精度,并且很大程度上减少了运算量。采用机载SAR原始数据验证了该算法的有效性。该算法对于高分辨率SAR的大量数据的实时成像处理,具有较大的应用价值。     

基于H.264编码的多屏共享系统研究

H.264/AVC是一种由ITU-T视频编码专家组合ISO/IEC JTC1动态图像专家组联合提出的高度压缩视频编码器标准。然而H.264/AVC编码器较高的运算复杂度提高了多屏共享系统的延迟时间。H.264/AVC由多种开源的实现,其中X264因简单高效而得到广泛的应用。在此对多频共享系统的关键技术进行实现,分析X264编码器提供的运动估计算法并且提出一种优化的算法。实验表明,新的算法提高了编码的速度、减少了系统延迟时间,同时视频质量几乎没有产生损失。     

An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization

In this paper, a highly efficient inter-interpolation architecture for the H.264/AVC standard is proposed. Since the placement order of frame pixels in the memory is either row-wise or column-wise which may not be suitable for the sample prediction in particular direction, this paper proposes a novel interpolator design which can dynamically configure the data-path for different predicted modes to perform proper computation schedules suitable for the nature input order of reference samples. The proposed design methodology not only can avoid the additional data transposition buffer, but most importantly the data transfer time spent to fetch the reference samples can be overlapped with the data computation time. Furthermore, by decomposing the chroma interpolation into a series of shift and addition operations, both luma and chroma interpolations can be integrated within the same module. In addition to the data-path design, this paper also proposes a new data-reuse buffer design based on a two-dimensional cache architecture to explore the possible data reuse among the inter and intra partitions. This design can be easily integrated with the H.264 interpolator to reduce the enormous demand of memory access. Our experimental results shows that our saving of memory bandwidth can be 23% more than what the best design can achieve by exploring the intra-partition data reuse only. The proposed design methodology has been implemented, and the result shows that the proposed interpolation architecture is the most compact design among the literatures which can perform the real-time H.264 video decoding with resolution up to 1920×1088 high-definition television standard. The proposed interpolator can be applied to the dedicated H.264 hardware codec design for various consumer devices.

Encoder adaptable difference detection for low power video compression in surveillance system

As a state-of-the-art video compression technique, H.264/AVC has been deployed in many surveillance cameras to improve the compression efficiency. However, it induces very high coding complexity, and thus high power consumption. In this paper, a difference detection algorithm is proposed to reduce the computational complexity and power consumption in surveillance video compression by automatically distributing the video data to different modules of the video encoder according to their content similarity features. Without any requirement in changing the encoder hardware, the proposed algorithm provides high adaptability to be integrated into the existing H.264 video encoders. An average of over 82% of overall encoding complexity can be reduced regardless of whether or not the H.264 encoder itself has employed fast algorithms. No loss is observed in both subjective and objective video quality.     

Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension

In addition to coding efficiency, the scalable extension of H.264/AVC provides good functionality for video adaptation in heterogeneous environments. Fine grain scalability (FGS) is a technique to extract video bitstream at the finest quality level under the given bandwidth. In this paper, an architecture of FGS encoder with low external memory bandwidth and low hardware cost is proposed. Up to 99% of bandwidth reduction can be attained by the proposed scan bucket algorithm, early context modeling with context reduction, and first scan pre-encoding. The area-efficient hardware architecture is implemented by layer-wise hardware reuse. Besides, three design strategies for enhancement layer coder are explored so that the trade-off between external memory bandwidth and silicon area is allowed. The proposed hardware architecture can real-time encode HDTV 1920×1080 video with two FGS enhancement layers at 200 MHz working frequency, or HDTV 1280×720 video with three FGS enhancement layers at 130 MHz working frequency.     

Geometrically determining the leaky bucket parameters for video streaming over constant bit-rate channels

For streaming of pre-encoded bitstreams over constant bit rate (CBR) channels, the channel bandwidth, the receiver buffer capacity as well as the latency requirement vary greatly from application to application. In this paper, we attempt to determine the minimum buffer size and the minimum start-up delay required for streaming a pre-encoded bitstream over CBR channels at any specific bit rate. The proposed method employs geometric operations to derive the optimal determination for low or high bit rates and sub-optimal determination for medium bit rates. The algorithm developed requires little extra information from the encoder and is easy to implement. Our algorithm is implemented in a H.264/AVC video encoder and its performance is compared with that of H.264/AVC hypothetical reference decoder. Our approach provides new theoretical insight and an excellent solution for determining the leaky bucket parameters for video streaming over CBR channels.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

Bandwidth Optimized and High Performance Interpolation Architecture in Motion Compensation for H.264/AVC HDTV Decoder

In this paper, we present high performance motion compensation architecture for H.264/AVC HDTV decoder. The bottleneck of efficient motion compensation implementation primarily rests on the high memory bandwidth demand and six-tap fractional interpolation complexity. To solve the bottleneck for H.264/AVC HD applications, three combined bandwidth optimization strategies are proposed to minimize the memory bandwidth for MB-based decoding process. To improve the interpolation hardware utilization and reduce the interpolation cycles, an interpolation classification scheme is proposed. By classifying the fifteen fractional pixels into five types and processing correspondingly, the interpolation cycles decrease significantly. A direct mapping memory cache characterized with circular addressing, byte-aligned addressing and horizontal and vertical parallel access is designed to support the proposed scheme. The hardware of proposed motion compensation is implemented at 100 M with 31.841 K logic gates, averagely 70–80% reduced memory bandwidth can be offered and the interpolation hardware can be fully utilized and interpolate one MB within 304 cycles, which can satisfy the real time constraint for H.264/AVC HD (1,920 × 1,088) 30 fps decoder. The design is implemented under UMC 0.18 μm technology, and the synthesis results and comparisons are shown.

H.264帧间模式选择优化算法

提出一种新的H.264快速模式选择算法：根据块的细节程度和纹理方向选择不同模式集，这些模式集比整个模式集模式数量大大减小，从而提高了模式搜索速度。信噪比的降低与比特率的增加都在可接受范围内，仿真结果证明了算法的有效性。     

Rate control for consistent visual quality of H.264/AVC encoding

In this paper, a novel rate control scheme with sliding window basic unit is proposed to achieve consistent or smooth visual quality for H.264/AVC based video streaming. A sliding window consists of a group of successive frames and moves forward by one frame each time. To make the sliding window scheme possible for real-time video streaming, the initial encoder delay inherently in a video streaming system is utilized to generate all the bits of a window in advance, so that these bits for transmission are ready before their due time. The use of initial encoder delay does not introduce any additional delay in video streaming but benefits visual quality as compared to traditional one-pass rate control algorithms of H.264/AVC. Then, a Sliding Window Buffer Checking (SWBC) algorithm is proposed for buffer control at sliding window level and it accords with traditional buffer measurement of H.264/AVC. Extensive experimental results exhibit that higher coding performance, consistent visual quality and compliant buffer constraint can be achieved by the proposed algorithm.     

Fast mode decision algorithm for H.264 inter-prediction

A fast mode decision algorithm for H.264/AVC inter-prediction to reduce computational complexity of the H.264 encoder is presented. Experimental results show that the algorithm can save the entire encoding time by 77% on average while introducing only negligible loss in PSNR value and small increment of bit rate.