Si/a-Si:H异质结微波双极型晶体管实验研究

本文首次报道采用重掺杂的氢化非晶硅(n~+a-Si∶H)作发射极的硅微波双极型晶体管的制备和特性.该器件内基区方块电阻2kΩ/□,基区宽度0.1μm,共发射极最大电流增益21(V_(cB)=6V,I_c=15mA),发射极Gummel数G_B值已达1.4×10~(14)Scm~(-4).由S参数测得电流增益截止频率f_s=5.5GHz,最大振荡频率f_(max)=7.5GHz.在迄今有关Si/a-Si HBT的报道中,这是首次报道可工作于微波领域里的非晶硅发射极异质结晶体管.     

低电压C类SiGe微波功率异质结双极型晶体管

给出了低电压微波 Si Ge功率异质结双极型晶体管 (HBT)的器件结构和测试结果 .器件结构适于低压大电流状态下应用 .采用了梳状发射极条的横向版图设计 ,其工作电压为 3— 4V.在 C类工作状态 ,1GHz的工作频率下 ,输出功率可以达到 1.6 5 W,具有 8d B的增益 . 3V时可以达到的最高收集极效率为 6 7.8% .     

低电压C类SiGe微波功率异质结双极型晶体管

给出了低电压微波SiGe功率异质结双极型晶体管(HBT)的器件结构和测试结果.器件结构适于低压大电流状态下应用.采用了梳状发射极条的横向版图设计,其工作电压为3-4V.在C类工作状态,1GHz的工作频率下,输出功率可以达到1.65W,具有8dB的增益.3V时可以达到的最高收集极效率为67.8%.     

垂直发射极镇流电阻在HBT中的发射极电流集边效应中的作用

在异质结双极晶体管(HBT)功率器件中可以引入外延生长的发射极镇流电阻,以改善其热稳定性.通过理论计算和实验表明这种低掺杂的外延层不仅能作为镇流电阻,而且在功率HBT器件中还能非常有效地降低发射极电流集边效应.     

垂直发射极镇流电阻在HBT中的发射极电流集边效应中的作用

在异质结双极晶体管(HBT)功率器件中可以引入外延生长的发射极镇流电阻,以改善其热稳定性.通过理论计算和实验表明这种低掺杂的外延层不仅能作为镇流电阻,而且在功率HBT器件中还能非常有效地降低发射极电流集边效应.     

射频功率HBT热稳定性的一种新表征方法

从热电反馈网络角度出发,在考虑到晶体管发射极电流随温度的变化、发射结价带不连续性（△Ev）、重掺杂禁带变窄（△Eg）及基极和发射极加入镇流电阻（RB和RE）等情况下,首次较全面地给出了功率晶体管热稳定因子S表达式。用该表达式可以很方便、明了地对功率双极晶体管进行热稳定性分析。分析了镇流电阻对射频功率晶体管安全工作区以及S的影响。结果表明,功率异质结双极晶体管（HBT）热稳定性优于同质结双极晶体管（BJT）,适当选取RB和RE可使S=0,使由器件本身产生的耗散功率而引起的自加热效应被完全补偿,器件特性得以保持,不因自热而产生漂移,这是同质结器件所无法实现的。     

南京大学和加州大学开发出用于高线性RF功放的新复合晶体管

要求达到高线性的放大器电路常采用预失真法。而中国南京大学声学院现代声学国家重点实验室和美国加尼福尼亚大学的研究人员开发出一种预失真发生在器件级的新复合晶体管器件。这种新晶体管拓朴结构基于采用一个标准的异质结双极晶体管器件和另外一个倒装型异质结双极晶体管,其集电极电阻用作预失真电路。这个集电极电阻连接到标准多指功率晶体管基极上。随着输入RF功率提高,上述功率晶体管基极到发射极的输入电压将减小,因而给功率晶体管的电流也就更大,补偿了输入电压减小。因此,采用这种预失真技术,因较低跨导引起的振幅失真在较高的RF…     

新型二维电子气Si/N~+α-Si:H异质结双极型晶体管

<正> 本文报道一种新型二维电子气异质结双极型晶体管(2DEG HBT)的实验结果。所谓2DEG HBT指的是采用宽禁带发射极材料的异质结双极型晶体管(HBT),由于发射结导带差等原因在异质结界面处形成二维电子气层,从而降低了对异质结界面态的要求,实现使用常规工艺来制作宽禁带发射极异质结晶体管。目前这一工作主要在硅材料上进行,利用重掺杂N型氢化非晶硅(N~+a-Si:H)作宽禁带发射极材料,在单晶硅上制作2DEG HBT。实验样管电流增益h_(FE)=120(V_(CE)5V,I_C=80mA),基区电阻5kΩ/□,表面浓度1.8×10~(18)cm~(-3)。     

非均匀条间距结构功率SiGe HBT

成功研制出非均匀发射极条间距功率SiGe异质结双极晶体管(HBT)用以改善功率器件热稳定性.实验结果表明,在相同的工作条件下,与传统的均匀发射极条间距HBT相比,非均匀结构HBT的峰值结温降低了22K.在不同偏置条件下,非均匀结构SiGe HBT均能显著改善芯片表面温度分布的非均匀性.由于峰值结温的降低以及芯片表面温度分布非均匀性的改善,采用非均匀发射极条间距结构的功率SiGe HBT可以工作在更高的偏置条件下,具有更高的功率处理能力.     

非均匀条间距结构功率SiGe HBT

成功研制出非均匀发射极条间距功率SiGe异质结双极晶体管(HBT)用以改善功率器件热稳定性.实验结果表明,在相同的工作条件下,与传统的均匀发射极条间距HBT相比,非均匀结构HBT的峰值结温降低了22K.在不同偏置条件下,非均匀结构SiGe HBT均能显著改善芯片表面温度分布的非均匀性.由于峰值结温的降低以及芯片表面温度分布非均匀性的改善,采用非均匀发射极条间距结构的功率SiGe HBT可以工作在更高的偏置条件下,具有更高的功率处理能力.     

Amorphous-Si emitter heterojunction UHF power transistors for handytransmitter

A UHF silicon heterojunction bipolar power transistor with a heavily doped amorphous-silicon emitter is reported. The fabrication process utilized an improved glow discharge technique. The deposition rate of amorphous silicon is 0.3-0.4 Å/s, which is slower than that of conventional a-Si:H. The average carrier density in the amorphous-silicon film is estimated to be about 1.5×10¹⁹ cm^-3. The present device can deliver 4.0-W output power with 72% collector efficiency and 8.2-dB gain at 470 MHz for 9.0-V low supply voltage. These preliminary results make the use of n⁺ a-Si:H as a wide-bandgap emitter material for high-frequency and high-power heterojunction bipolar transistors (HBTs) very attractive     

The silicon-on-sapphire MOS tetrode—Some small-signal features, LF to UHF

This paper describes the structure and performance of a silicon-on-sapphire (SOS) dual-gate MOSFET-the SOS MOS tetrode. Extremely low-drain capacitance, negligible parasitics, and the absence of a semiconducting substrate make the device very attractive as a building block in UHF integrated systems. I-V characteristics are shown, and a simple small-signal model that is useful up to tens of megahertz is described. The expressions for the output resistance and gain functions for both gates are given. The UHF y-parameters for the tetrode are derived, based upon Hopkins' accurate UHF model for the MOS triode, utilizing the cascode configuration. The important parameters and the unilateral power gain are examined, and compared with measured values. Measurements confirm the extended UHF performance, negligible reverse transadmittance, and high-unilateral power gain. Variations of the y-parameters with bias are examined; low-frequency voltage gain factor, µ, and UHF power gain, Gp, are compared as functions of gate voltage. All derivations assumed f = 500 MHz as the frequency of interest but appear to be valid up to low gigahertz range.     

应用于无源UHF RFID传感器接口的低功耗低压转换器设计

为了增加射频识别（RFID）传感器的识读范围,针对无源超高频（ultra high frequency,UHF）RFID标签的传感器接口,提出了一种新的低功耗低压时间数字转换器设计。该传感器接口采用基于游标原理的高效时数转换器,在保证分辨率和转换效率的同时,能够实现较低的功耗和较大的动态范围。采用TSMC 90nm标准CMOS技术设计并制造。测量结果显示相比其他类似结构,提出接口在输入时间范围28.18-42.94 时有效分辨率为10.48bits。采样率为20 KS/s时,转换器转化效率为0.396 pJ/bit,且功耗和电压供应分别仅为3.84 和0.6V,能够有效增强无源UHF RFID压力传感器标签的识读范围。     

应用于无源超高频射频识别卡芯片的能量提取电路建模与分析

Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.     

Modeling and analysis of power extraction circuits for passive UHF RFID applications

Modeling and analysis of far field power extraction circuits for passive UHF RF identification (RFID) applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear ap-proximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.     

A high-speed low-power tri-state driver flip flop for ultra-lowsupply voltage GaAs heterojunction FET LSI's

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage, which is 1/5 of the minimum value reported for D-FFs so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage     

新型SiGe/Si异质结开关功率二极管的特性分析及优化设计

将SiGe技术应用于功率半导体器件的特性改进,提出了新型Si Ge/Si异质结p-i-n开关功率二极管结构,在分析器件结构机理的基础上,用Medici模拟了该器件的特性并进行了优化设计.结果表明,该功率二极管具有低的正向压降,较少的存贮电荷,其性能远远超过Si的同类型结构.这种性能的改进无需采用少子寿命控制技术,因而很容易集成于功率IC中.     

一种用于UHF RFID标签的超低功耗数字处理机设计

A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.     

A Fully Integrated UHF CMOS Power Amplifier for Spacecraft Applications

A power amplifier (PA) is designed for a surface-to-orbit proximity link microtransceiver on Mars exploration rovers, aerobots, and small networked landers and works in conjunction with a 0.2-dB loss transmit/receive switch to allow nearly the full 1 W to reach the antenna. The fully integrated UHF CMOS PA with more than 30-dBm output is reported for the first time. A differential pMOS structure with floating-bias cascode transistors and 1:3-turn ratio output transformer are chosen to overcome low breakdown voltage (V _bk) of CMOS and chip area consumption issues at UHF frequencies. The high-Q on-chip transformer on a sapphire substrate enables the differential PA to drive a single-ended antenna effectively at 400 MHz. The PA in a standard package delivers 30-dBm output with 27% power-added efficiency. No performance degradation was observed in continuous-wave operation and the design has been tested to 136% of its nominal 3.3-V supply without failure.     

带新解调结构的UHF RFID标签低功耗模拟前端设计

基于ISO/IEC 18000-6C协议,对UHF无源电子标签模拟前端中的ASK解调电路、整流器、稳压电路等进行低功耗设计。解调电路中微分电路的加入扩大了解调电路工作范围,在解调电路近距离工作时,可以更有效地解调。整流电路采用了零阈值MOS管代替肖特基二极管,降低芯片成本。整流稳压电路可稳定地为芯片供电,供电电压2 V,建立时间仅为25μs。电路采用SMIC 0.18μm 2P4M CMOS工艺进行流片,芯片面积720μm×390μm。测试得到模拟前端整体工作电流仅2.4μA,标签工作距离大于7 m。