Improved thermal characterization method of integrated microscale heat sinks

The thermal management of semiconductor devices is still a hot topic. Most designers, who are aware of the thermal aspects of IC design, know that new, cheaper and more efficient methods are required to keep the temperature of electronic systems low. Research by different teams regarding the cooling of stacked die structures is in progress.In this paper an improved thermal characterization method will be presented to determine the flow dependent partial thermal resistance of integrated microchannel based heat sinks. This reliable characterization method does not demand thermal isolation during the measurements, only constant environment conditions. The measurements are based on the industrial standard thermal transient testing method.On the other hand we present an approach to realize an integrated microfluidic channel based heat sink, which can be realized in the backside of the silicon chip itself. The approach is based on a cheap wet etching process instead of reactive ion etching or LIGA technologies, which enables batch processing.     

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach.     

Maximising energy efficiency in 3D multicore systems: a formalised approach

Three-dimensional integrated circuits (3D ICs) present an intriguing challenge for both circuit and system engineers due to their diverse cooling efficiency among the stacked dies. Several recent proposals advocate multiple techniques for thermal management of 3D ICs at different levels of the design, while operating within the confines of thermal heterogeneity. In this article, we analyse for the first time, the role of thermal heterogeneity on the energy efficiency of the system by incorporating temperature dependent leakage power. We develop a novel convex optimisation framework to optimise the energy efficiency in 3D ICs incorporating: (a) leakage aware thermal provisioning using temperature dependent full-chip leakage model, (b) heat flow in vertically stacked systems using a grid based compact thermal model and (c) a concrete application for workload provisioning in 3D multicore systems. Detailed simulation-based experiments with our proposed optimisation framework shows 5–17% improvement in the energy efficiency of a typical multicore system organised as 3D stacked dies.     

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.     

Integrated electro-thermomechanical analysis of nonuniformly chip-powered microelectronic system

An integrated electrical, fluid flow and thermomechanical analysis is presented to study a product reliability and thermal management solution in an actual or nonuniform chip power distribution of an integrated circuit device in a realistic system application environment. This study aims to improve the existing limitations both on electrothermal analysis where simplified thermal boundary conditions is mostly used and on the current thermal and fluid flow analysis where uniform chip power is widely used to calculate the temperature. In this approach, the localized on-chip power distribution is obtained by using a transistor-level circuit model for simulating the interaction between the macro and functional blocks. A computational fluid dynamics analysis is used to calculate the fluid flow and heat transfer solution with a realistic thermal boundary conditions. To address the ultimate thermal induced mechanical stress and reliability effects on the chip-packaged assembly due to the nonuniform chip power distribution, finite element model is employed for the sequential steady-state heat transfer and mechanical analysis. The results are then discussed and specifically compared with the solutions based on the uniform chip power conditions.     

HotSpot: a dynamic compact thermal model at the processor-architecture level

This paper describes a thermal-modeling approach that is easy to use and computationally efficient for modeling thermal effects and thermal-management techniques at the processor architecture level. Our approach is based on modeling thermal behavior of the microprocessor die and its package as a circuit of thermal resistances and capacitances that correspond to functional blocks at the architecture level. This yields a simple compact model, yet heat dissipation within all major functional blocks and the heat flow among blocks and through the package are accounted for. The model is parameterized, boundary- and initial-conditions independent, and is derived by a structure assembly approach. The architecture community has demonstrated growing interest in thermal management, but currently lacks a way to model on-chip temperatures in a tractable way. Our model can be used for initial exploration of the design space at the architecture level. The model can easily be integrated into popular power/performance simulators, can be used to determine how thermal stress is correlated to the architecture, and how architecture-level design decisions influence thermal behavior and related effects.     

某空间气体监测仪热设计及试验验证

某空间气体监测仪结构布局紧凑,在较小尺寸空间内交错布置有8个镜头组件、11台电子设备内热源和2个电机。内热源数量众多,工作时间长,与镜头控温要求差别大,且1个电机为二维转动热源,这些特点给热设计带来挑战。为有效解决热控难题,采用了多种设计思路组合。基于热管理思路对监测仪各部组件热行为进行系统管理,以节省热控资源;基于间接热控思路对所处热环境复杂的光学镜头组件进行控温,提高其控温精度和温度稳定度;对转动电机则进行辐射冷却,避免在传热路径中引入挠性转动环节,以提高热控系统可靠性;并基于结构热控一体化设计,在结构上充分保证热设计各项需求。热平衡试验结果表明:高低温工况下,监测仪各部组件温度均满足指标要求,且整个寿命周期内,光学镜头温度稳定度较高,同一工况下光学镜头最大温度波动在1℃以内,实现了多热源复杂工作机制下光学镜头的高精度精密热控。     

Functional Soft Composites As Thermal Protecting Substrates for Wearable Electronics

Thermal management of wearable electronics integrated with biological tissues remains one of the critical challenges for their practical applications. The undesired heating can cause thermal discomfort or even thermal damage to biological tissues. Here, a novel thermal protecting substrate design is proposed for wearable electronics with abilities to manipulate the heat flow and efficiently absorb the excessive heat energy without the compromise of substrate flexibility. The thermal protecting substrate features a functional soft composite, which incorporates the embedded phase change material with a thin metal film on the top in a soft polymer. Compared with conventional substrate, the proposed thermal protecting substrate can reduce the peak temperature increase by over 85% with appropriate parameters. Experimental and numerical studies reveal the fundamental aspects of the design and operation of functional soft composite to effectively avoid excessive heating of biological tissues. Influences of geometrical parameters on temperature reduction are investigated. Device demonstration of thermal protecting substrate in a wearable heater on pig skin illustrates the unusual capability to reduce the maximum skin temperature, thereby enabling practical applications of wearable electronics and creating engineering opportunities in biointegrated applications requiring thermal protection of biological tissues.     

Heat dissipation design and analysis of high power LED array using the finite element method

High-power Light Emitting Diode (LED) technology has developed rapidly in recent years from illumination to display applications. However, the rate of heat generation increases with the LED illumination intensity. The LED chip temperature has an inverse proportion with the LED lifetime. High-power LED arrays with good thermal management can have improved lifetime. Therefore, for better optical quality and longer LED lifetime it is important to solve the LED thermal problems of all components. In particular, Metal Core Printed Circuit Board (MCPCB) substrate heat sink design and thermal interface materials are key issues for thermal management. This paper presents an integrated multi-fin heat sink design with a fan on MCPCB substrate for a high-power LED array using the finite element method (FEM). The multi-fin heat sink design and simulation results provide useful information for LED heat dissipation and chip temperature estimation.     

A simulation study of IC layout effects on thermal management ofdie attached GaAs ICs

Power management and thermal characterization of integrated power amplifiers is crucial to the development of a number of advanced technologies including portable wireless applications. Reduction and or optimization of device operating temperatures and thermal characteristics is needed to control temperature activated failure phenomena. This paper presents the use of PATRAN, a three-dimensional (3-D) model builder and finite element method (FEM) solver as means of understanding the heat flow in integrated devices and optimizing the layout for thermal operation. The approach taken is to assume a priori knowledge of the heat generation region and decouple the semiconductor transport equations. This allows for solution of the heat equation over a sufficiently large region to be correct. After verifying the correctness of the assumption of the device temperature being relatively insensitive to the depth, thickness and shape of the heat generation region, the optimization of heat spreaders in a GaAs HBT process is presented. This optimization is performed as an example of how both the maximum temperature and temperature variation across the emitter can reduced by careful design of the emitter metallization. Finally, the use of PATRAN is presented for extracting a three resistor thermal model for two devices in close proximity     

ATM traffic management considerations for facilitating broadbandaccess

Traffic management in ATM nodes plays a key role in providing the capability to support a wide range of integrated services while utilizing network resources, such as buffer space and bandwidth, in an efficient manner. In many cases, the issues arising in ATM access devices are very similar to those encountered in larger ATM backbone nodes. In this article, major issues in the design of traffic management schemes are discussed. These include switch fabric design, buffering strategies, service scheduling disciplines, usage parameter control, buffer management schemes, call admission control, and feedback flow control     

Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs

Thermal hot spots and high temperature gradients degrade reliability and performance, and increase cooling costs and leakage power. In this paper, we explore the benefits of temperature-aware task scheduling for multiprocessor system-on-a-chip (MPSoC). We evaluate our techniques using workload characteristics collected from a real system by Sun's Continuous System Telemetry. We first solve the task scheduling problem statically using integer linear programming (ILP). The ILP solution is guaranteed to be optimal for the given assumptions for tasks. We formulate ILPs for minimizing energy, balancing energy, and reducing hot spots, and provide an extensive comparison of their thermal behavior against our technique. Our static solution can reduce the frequency of hot spots by 35%, spatial gradients by 85%, and thermal cycles by 61% in comparison to the ILP for minimizing energy. We then design dynamic scheduling policies at the OS-level with negligible performance overhead. Our adaptive dynamic policy reduces the frequency of high-magnitude thermal cycles and spatial gradients by around 50% and 90%, respectively, in comparison to state-of-the-art schedulers. Reactive thermal management strategies, such as thread migration, can be combined with our scheduling policy to further reduce hot spots, temperature variations, and the associated performance cost.      

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor

Due to the aggressive scaling of process technologies, ultra-logic densities on integrated circuits, and also the complexity of designs, which in turn lead to a drastic increase of power density, thermal issues have become a bottleneck in electronics designs, result in a new focus for much researches over last years. To address this issue, various dynamic thermal management (DTM) techniques have been proposed to maintain the operation of systems safe and reliable. To effectively apply DTM techniques, providing a precise and reliable network of temperature sensors is highly required to measure local temperatures and provide an accurate thermal map of the chip. While many designers have utilized ring-oscillator (RO) circuits as temperature sensors in a network for measuring the thermal distribution and predicting the thermal behavior of a field programmable gate array (FPGA), a high-level study of the temperature sensors' design space is still missing. In this paper, a novel concept of the RO-based temperature sensor based on four basic evaluation metrics is presented. We introduce four useful evaluation metrics (i.e. the area, thermal, and power overheads, and thermal map error) and some measurement methods for exploring and comparing the relative performance of different temperature sensor's designs. Then, in order to make an optimal choice based on the metrics obtained, we propose a figure of merit (FOM) to characterize the efficiency of these designs. The proposed performance evaluation metric, the quality factor (QF), is based on the overheads and measurement accuracy trade-offs between different designs of the RO-based temperature sensor. Consequently, the proposed QF metric is a quantity value representing a measure of effectiveness, efficiency, and performance of a temperature sensor network, which can help the designer to make a proper decision. Moreover, in this work, a compact and ultra-sensitive RO-based temperature sensor is presented that utilizes only 5 look-up tables (LUTs), occupies 37.5% fewer resources than the most compact sensor, and provides 2.72 times higher sensitivity than the best sensitive design. Also, in this paper, several designs of the RO-based temperature sensor are explored in a network, in terms of various sensor's configurations, RO length, and counter width, and compared with each other in order to investigate their influences on the efficiency of the sensor network. According to the QF metric and experimental results, the sensor network based on the proposed sensor has the best efficiency among other alternative designs.     

Thermal management for high-power photonic crystal light emitting diodes

An effective heat dissipation structure is a crucial element for stable thermal management in ensuring thermal stability of high power photonic crystal light emitting diodes (PC-LEDs). New integrated structure for effective thermal management is put forward for high power PC-LEDs to reduce the thermal resistance between the chip and heat dissipation device, which can be composed by the heat pipes or an active heat dissipation device. Based on the thermal resistances analyzed, 3D thermal distributions for the device CSM360 with the nominal electric power of 80 W are simulated and analyzed by using of ANSYS. Compared with the general metal fins model, the heat pipes integrated model improves the heat dissipation efficiency of CSM360 by 36.61%, while the active heat dissipation device integrated model improves the heat dissipation efficiency by 60.2% at the temperature of 50 °C on the cold end of the device. The results show that the integrated structure can obtain a significant improvement in thermal management and achieve a reduction in temperature in the working status of CSM360. Heat dissipation experiments are also conducted, and the values of temperature distributions are validated to be coincident with those from simulations.     

星载SAR相控阵天线一体化热设计

介绍了星载相控阵天线一体化热设计的方法,利用不同的仿真软件分析了天线热分布、结构变形等情况,通过建立热变形对天线电性能影响的仿真模型,验证热设计是否能满足电性能要求,并以电性能最优为目标实现最优的热设计。最后,针对星载SAR天线产品验证文中设计方法的工程可实现性。     

On the modeling of the transient thermal behavior of semiconductordevices

A mathematical model of the transient temperature response of integrated devices is presented which takes into account the three-dimensional (3-D) nature of heat flow and the physical structure of the device. Simple analytical relations for the transient thermal impedance and thermal time constants are derived for the first time. The impact of device geometry on the transient thermal response curve is discussed, and simple guidelines for the thermal design of solid-state devices operated in transient or pulsed regime are given     

A Dynamic Thermal Management Circuit for System-On-Chip Designs

A novel fully integrated dynamic thermal management circuit for system-on-chip design is proposed. Instead of worst-case thermal management used in conventional systems, this design yields continual monitoring of thermal activity and reacts to specified conditions. With the above system, we are able to incorporate on-chip power/speed modulation and integrated multi-stage fan controllers, which allows us to achieve nominal power dissipation and ensure operation within specification. Both architecture and circuitry are optimized for modern system-on-chip designs. This design yields intricate control and optimal mangement with little system overhead and minimum hardware requirements, as well as provides the flexibility to support different thermal mangement algorithms.