Electrical characteristics of Be-implanted GaAs activated by rapid thermal annealing

Be-implanted GaAs are annealed by rapid thermal annealing (RTA) using halogen lamps. Electrical properties of the annealed GaAs are investigated, emphasizing those at 77K for application to the p+-layer of Be-implanted WSix-gate self-aligned two-dimensional hole gas (2- DHG) FET. An electrical activation of 90 percent (for 2.0 × 10¹³cm^-2) or 80 percent (for 2.2 × 10¹⁴cm^-2) is obtained. An annealing temperature dependence of carrier freezing at 77K is observed for higher dose samples. The phenomenon is attributed to the redistribution of impurity atoms near the high-concentration peak.     

n-channel MOS transistors in mercury—cadmium—telluride

n-channel MOS transistors operating at 77 K have been realized in Hg0.71Cd0.29Te with ion-implanted source and drain junctions. Enhancement-mode transistors were made with evaporated ZnS as a gate insulator, and depletion-mode transistors were made using a native oxide of mercury-cadmium-telluride. The devices exhibit surface mobility as high as 1.5 × 10⁴cm². V^-1. s^-1. Current-voltage characteristics and capacitance-voltage data are presented and analyzed.     

1—2-keV Boron implants into silicon

1000-Å-A thick heavily doped layers have been produced in Si by implanting B at energies as low as 1-2 keV. No preamorphization is required and the near-surface random peak is redistributed by diffusion into the deeper channeled region to provide sharp junctions. Doping levels of ∼ 2 × 10²⁰cm^-3can be maintained over a region ∼600-Å-thick while maintaining junction depths as shallow as 1000 Å.     

Temperature dependence of breakdown voltage in silicon abrupt p-n junctions

Temperature dependence of breakdown voltage in silicon abrupt p⁺-n junctions has been calculated using a modified Baraff theory [1]-[3] and measured experimentally from 77°K to 500°K, with substrate doping from 10¹⁵cm^-3to 10¹⁸cm^-3. Experimental data are in good agreement with the results of theoretical calculations. These results strongly substantiate the validity of the modified Baraff theory which has been pointed out by Sze and Crowell.     

Source—Drain contact resistance in CMOS with self-aligned TiSi2

The contact resistance between TiSi2and n⁺-p⁺source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10^-7and 1 × 10^-6Ω . cm²can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10²⁰/cm³. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi2-n⁺and TiSi2-P⁺interfaces.     

Heavy doping effects in p-n-p bipolar transistors

This paper presents the heavy doping effects on the injection current characteristics in p-n-p transistors with a heavily doped but thin base region. The results of the present study indicate that 1) at room temperature the hole current injected into heavily doped base is insensitive to the impurity compensation effect, 2) a linear relationship between the base sheet resistance and the collector-current density is observed when the base doping density is under 1 × 10¹⁹cm^-3. This relationship becomes supralinear as the doping density further increases. As a result, useful current gain exists in thin base transistors even when the base doping is greater than 1 × 10¹⁹cm^-3. From the collector-current-base sheet-resistance relationship and the base doping profile, the effective intrinsic carrier density as a function of the doping density is evaluated and found to increase 8.7 times over that of pure silicon, when the average doping density is 5 × 10¹⁹cm^-3(maximum doping density 1 × 10²⁰cm^-3). 3) The collector current and the current gain of the transistors become less sensitive to the temperature as the base doping density increases. We had observed a current gain up to 30 at 77 K for transistors with the maximum base doping density in the 10¹⁸cm^-3range. The transistors with lower base doping suffer much more degradation in current gain when the temperature is lowered to 77 K.     

Device characterization of p-channel AlGaAs/GaAs MIS-like heterostructure FET's

p-channel AlGaAs/GaAs MIS-like heterostructure FET's (p-MIS HFET's) are characterized concerning their gate-source leakage current. Device performance is confirmed to improve approximately inversely to layer thickness dtbetween the channel and metal gate, at low gate voltages. A high transconductance gmof 110 ms. mm-1is obtained at 77 K by reducing dtto 20 nm. Maximum transconductance is limited by gate-source leakage current Igs. Igsis governed mainly by the leakage current through the ion-implanted gate edge and is reduced by decreasing the dose level of ion-implantation at the gate edge to 2 × 10¹³cm^-2. The contact resistance is reduced to about 0.1 ω. mm by ion implantation into the ohmic contact region to a dose of 2 × 10¹⁴cm^-2. Calculations indicate that, by reducing Igsand the gate-source resistance to 1 ω. mm with the lightly doped drain (LDD) structure, gmaround 200 mS. mm^-1at 300 K and 300 mS. mm^-1at 77 k are achievable with a 1-µm gate structure.     

Channeling depth distributions of Be and Si in GaAs as a function of implantation energy and fluence

Be and Si are commonly employed p- and n-type respectively dopants, implanted in GaAs. Channeled implantation produces deeper and sharper profiles than standard random implants. To employ channeling, we need to know how the profile shape, depth, and doping density vary with implantation energy and fluence, and what maximum density can be achieved. This work shows how channeling profiles in the direction of GaAs vary with energy and fluence for room temperature channeling. Data are shown for fluences of 3 × 10¹², 3 × 10¹³, and 3 × 10¹⁴cm^-2and energies of 40, 75, 150, and 300 keV. The deep channeling profile saturates for 150 keV Be just below a fluence of 3 × 10¹⁴cm^-2and a density of about 4 × 10¹⁷cm^-3can be achieved at depths of about 1 to 3 µm for energies from 75 to 300 keV. The maximum density for 150 keV Si for room temperature channeling is about 4 × 10¹⁶cm^-3and occurs at depths from 1 to 4 µm in the energy range from 40 to 300 keV.     

Very-shallow low-resistivity p+-n junctions for CMOS technology

Shallow p-n junctions 110 nm deep have been fabricated using rapid thermal diffusion from a spin-on oxide source. Surface concentrations greater than 3 × 10²⁰cm^-3are possible, with sheet resistivities less than 100 Ω/sq and a maximum reverse-bias leakage at 5 V of 3 nA.cm^-2. Results from 150-nm junctions are also given and are compared with BF2ion implantation.     

High-voltage planar p-n junctions

A concentric ring junction has been devised to prevent surface breakdown of a planar junction. By properly choosing the spacing between the main junction and the ring, the ring junction acts like a voltage divider at the surface. In addition, the ring junction minimizes the effect of the junction curvature at the periphery of a planar junction. Devices fabricated with three such rings showed breakdown voltages of 2000 and 3200 volts on n-type silicon with impurity concentrations 6.5 × 10¹³and 2.5 × 10¹³cm^-3, respectively. That the structure operated as proposed was corroborated by comparison of the reverse leakage current with a one parameter fit to a theoretically calculated current obtained from the approximated volume of the space charge regions. These results together with the photo response measurements indicate that the field-limiting ring junction can be used successfully to obtain high-voltage planar p-n junctions.     

An investigation of i-AlGaAs/n-GaAs doped-channel MIS-like FET's (DMT's)—Properties and performance potentialities

Doped-channel MIS-like FET's (DMT's) based upon an i-AlGaAs/n-GaAs structure have been investigated in detail for the purpose of clarifying their properties and performance potentialities. The DMT is unique in having two operation modes, a depletion-layer modulation mode and an electron accumulation mode, both of which are experimentally demonstrated through capacitance-voltage characteristics. Analytical and experimental results shows that the maximum drain current IDSmaxis more than 2.5 times that for a conventional n-AlGaAs/GaAs 2DEGFET. gmmaxand IDsmaxvalues obtained for 0.5- µm gate DMT's are very high, 310 mS/mm (410 mS/mm) and 650 mA/mm (800 mA,/mm) at 300 K (77 K), respectively, fmaxis 48 GHz. fTis as large as 45 GHz, which is the best data ever reported in 0.5-µm gate FET's. Moreover, the estimated electron saturation velocity is outstandingly large, 1.5 × 10⁷cm/s (2 × 10⁷cm/s) at 300 K (77 K), even for a thin GaAs channel layer with a 3 × 10¹⁸cm^-3doping level, while Hall electron mobility is not reasonably so high, being typically 1850 cm²/V . s (1650 cm²/V . S). Preliminary power performances are also studied at 28.5 GHz. An 18-dBm (225-mW/mm) saturation output power, 6.4-dB linear gain, and 15-percent power added efficiency are achieved. A further performance improvement may be easily accomplished by gate length reduction, structure optimization, and so on. Consequently, it has been proved that DMT's have great feasibility for high-speed and high-frequency high-power device applications.     

A polysilicon—Silicon n-p junction

Phosphorus-doped polycrystalline silicon is grown in an epitaxial reactor by the reduction of a hydrogen-diluted silane-phosphine mixture passing over a substrate heated to 800°C. The influence of the phosphine-silane ratio on growth rate, electrical resistivity, active donor concentration, and Hall mobility is examined. It is found that phosphine inhibits growth rate at 800°C to a lesser degree than it does at lower growth temperatures. Growth rate progressively drops to 0.6 of the undoped value as the phosphine-silane ratio is increased to 10^-1. Resistivity drops from 1 to 10^-3Ω. cm as active phosphorus concentration varies between 10¹⁸and 4 × 10²⁰cm^-3, while Hall mobility rises from 4 to 30 cm²/ V.s. Diodes are formed between the grown polysilicon layers and the single-crystal p-type silicon substrates. They are found to have recombination currents critically dependent on the phosphine/ silane ratio during growth of the polysilicon. As this ratio increases above 10^-5, recombination decreases, while mobility in the polysilicon increases. These results support the "dopant segregation" theory of conduction in polysilicon. For ratios of 10^-3to 10^-2the diodes obtained showed a recombination factor approaching those of diffused diodes and are useful devices, for example, as the emitter-base junction of a shallow-base high-frequency, bipolar transistor.     

Effect of Hydrogen implantation on polysilicon p-n junctions

The effect of hydrogen implantation on theI(V)characteristics of lateral polysilicon p-n junctions is reported. After implantation with hydrogen and annealing at 400°C, a moderate decrease in the forward current and a large decrease in the reverse current is observed. In addition, the reverse breakdown voltage is increased. Best results were obtained for hydrogen dose of 10¹⁶cm^-2. The measurements are explained by considering both electric field enhancement of emission and capture rates and the generation of new trap levels by ion implantation.     

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10¹⁰cm^-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm². Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10¹⁰cm^-2.     

Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon

We correlate the work-function difference φps⁰between the polysilicon gate and the silicon substrate in an MOS system with the doping level and carrier concentration in polysilicon. Polysilicon was doped by ion implantation with arsenic and phosphorus. The doping level was varied from 10¹⁹to 10²⁰cm^-3. Hall measurements were used to determine the carrier concentration in polysilicon at a given doping level. The Hall mobility and resistivity as a function of doping level were also obtained. The work function difference φps⁰was determined by capacitance-voltage measurements on polysilicon-SiO2-Si capacitors with different oxide thicknesses. When plotted against the doping level, the work-function difference had a maximum at a dopant concentration of ≈ 5 × 10¹⁹cm^-3, which corresponds to an electron concentration of 1.5 × 10¹⁹cm^-3. At higher doping levels the value of φps⁰decreases. The results can not be fully understood in terms of the Si band structure.     

Counting of deep-level traps using a charge-coupled device

Quantization in dark current generation has been observed for the first time through the use of a virtual-phase charge-coupled device. Two sites for bulk silicon dark current have been identified with capture cross sections of 1.8 × 10^-15cm²and 5.4 × 10^-16cm², and concentrations of 1.3 × 10⁹cm^-3and 1.5 × 10⁸cm^-3, respectively.     

Incoherent annealing of implanted layers in GaAs

Incoherent light from filament lamps focused by elliptical mirrors has been used to activate implanted layers in GaAs. 4 × 10¹⁴Si⁺cm^-2and 2 × 10¹⁴Zn⁺cm^-2implants were annealed with Si3N4deposited by CVD at 400°C providing a surface protective layer. By taking advantage of the focusing properties of elliptical mirrors, most of the emitted light could be concentrated onto the GaAs to give annealing times × 1 sec. Differential Hall measurements show peak carrier concentrations of 6.5 × 10¹⁸cm^-3and 50% activation for the n+ layers. The Zn implants were completely activated and doped to ∼ 2 × 10¹⁹cm^-3. These results, together with the short annealing times, suggest the present approach to be an attractive alternative to both laser and conventional thermal annealing.     

Growth of high-purity semi-insulating bulk GaAs for integrated-circuit applications

Growth of high-purity bulk semi-insulating GaAs by the Liquid-Encapsulated Czochralski (LEC) method has produced thermally stable, high-resistivity crystals suitable for use in direct ion implantation. Large round substrates have become available for integrated-circuit processing. The implanted wafers have excellent electrical uniformity (±4 percent Vp) and have shown electron mobility as high as 4800cm²/V.s for Se implants with 1.7 × 10¹⁷cm^-3peak doping. Careful control of background doping through in situ synthesis has produced GaAs with Si concentrations as low as 6 × 10¹⁴cm^-3grown from SiO2crucibles. Detailed results of qualification tests for ion implantation in LEC GaAs will be discussed. Feasibility of successful high-speed GaAs large-scale integrated circuits using LEC substrates will be described.     

High-purity semi-insulating GaAs material for monolithic microwave integrated circuits

Liquid-Encapsulated Czochralski (LEC) growth of large-diameter bulk GaAs crystals from pyrolytic boron nitride (PBN) crucibles has been shown to yield high crystal purity, stable high resistivities, and predictable direct ion-implantation characteristics. Undoped (≲low 10¹⁴cm^-3chromium) and lightly Cr-doped (low 10¹⁵cm^-3range) -GaAs crystals, synthesized and pulled from PBN crucibles contain residual shallow donor impurities typically in the mid 10¹⁴cm^-3, exhibit bulk resistivities above 10⁷Ω . cm, and maintain the high sheet resistances required for IC fabrication (>10⁶Ω/□) after implantation anneal. Direct²⁹Si channel implants exhibit uniform (± 5 percent) and predictable LSS profiles, high donor activation (75 percent), and 4800- to 5000-cm²/V . s mobility at the (1 to 1.5) × 10¹⁷cm^-3peak doping utilized for power FET's. It has also been established that LEC crystals can provide the large-area, round     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature