A novel silicide nanopatterning method for the fabrication of ultra-short channel Schottky-tunneling MOSFETs

A novel nanometer patterning technique was developed to pattern epitaxial CoSi₂ layers and to fabricate Schottky-tunneling MOSFETs. The nanopatterning method is based on the local oxidation of silicide layers. A feature size as small as 50 nm was obtained for 20 nm epitaxial CoSi₂ layers on Si(100) after patterning by local rapid thermal oxidation in dry oxygen. A Schottky-tunneling MOSFET with epitaxial CoSi₂ Schottky contacts at both the source and the drain was fabricated using this nanopatterning method to make the 100 nm gate. The device shows good I–V characteristics at 300 K.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Schottky-clamped NMOS transistors implemented in a conventional0.8-μm CMOS process

An 0.8-μm n-channel MOSFET with a TiSi₂-Si Schottky clamped drain-to-body junction (SCDR) and an n⁺ implanted standard source structure have been fabricated in a conventional 0.8-μm salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n⁺-drain/p-substrate/n⁺-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n⁺ drain-to-p-substrate guard-ring diode connected in parallel     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Elevated n+/p junctions by implant into CoSi2formed on selective epitaxy for deep submicron MOSFETs

Very shallow elevated n⁺/p junctions formed by arsenic implant into or through cobalt silicide (CoSi₂) formed on selective epitaxial layers and their application to deep submicron n-channel MOSFETs were studied for the first time. PREDICT 1.6 simulation program was employed to choose the desired implant energies and annealing thermal cycle based on theoretically predicted silicide thickness. The implanted CoSi₂ elevated junctions had low reverse current and no bias voltage dependence up to 5 V. Diffusion current dominated the junction forward current, and good ideality factors close to 1 were obtained. A nearly abrupt junction doping profile was achieved. Deep submicron n-channel MOSFETs incorporating implanted CoSi₂ elevated junctions were demonstrated. Sharp turn-off and reasonably large drain currents were achieved     

One micrometre scale self-aligned cobalt disilicide Schottkybarrier diodes

CoSi₂/n-type silicon(111) Schottky barrier diodes on a 1 μm scale have been fabricated using a self-aligned silicide process incorporating magnetron sputtering and rapid thermal processing, in an industrial environment. Anneal temperatures in the range 700-1100°C have been used, and ideality factors of 1.06-1.07 were obtained in the range 700-900°C with larger values for higher temperatures. The consistency in the values of the ideality factor indicates that a wide annealing temperature window exists for the successful fabrication of CoSi₂/silicon diodes     

Ultra-shallow junction formation using silicide as a diffusionsource and low thermal budget

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide processing) of 45-nm CoSi₂ films (3.5 Ω/□) using a low thermal budget. The best junctions of either type were made by moderate 10-s RTA (rapid thermal annealing) at 800°C, where the total junction depth, counting the silicide thickness, is believed to be under 60 nm. Diffusion-limited current predominated down to 50°C in junctions made under these conditions. The initial implantation energy had only a minor effect on the junction leakage, where shallower implants required slightly higher temperatures to form low leakage diodes, resulting in diodes which were somewhat more susceptible to shorting during silicide agglomeration at high temperatures. The ITS scheme, where dopant is implanted slightly beyond the silicide, gives an equally low leakage current. Nevertheless, the ITS scheme gives deeper junctions than the SADS process, and it is difficult to control the position of the ITS junction due to silicide/silicon interface fluctuations     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

Simplified ohmic and Schottky contact formation for field effecttransistors using the single layer integrated metal field effecttransistor (SLIMFET) process

A new III-V semiconductor device fabrication process for GaAs-based field effect transistors (FET) is presented which uses a single lithographic process and metal deposition step to form both the ohmic drain/source contacts and the Schottky gate contact concurrently. This single layer integrated metal FET (SLIMFET) process simplifies the fabrication process by eliminating an additional lithographic step for gate definition, a separate gate metallization step, and thermal annealing for ohmic contact formation. The SLIMFET process requires a FET structure which incorporates a compositionally graded In_xGa_1-xAs cap layer to form low resistance, nonalloyed ohmic contacts using standard Schottky metals. The SLIMFET process also uses a Si₃N₄ mask to provide selective removal of the InGaAs ohmic layers from the gate region prior to metallization without requiring an additional lithographic step. GaAs MESFET devices were fabricated using this new SLIMFET process which achieved DC and RF performance comparable to GaAs MESFET's fabricated by conventional methods     

A manufacturable process to improve thermal stability of 0.25-μmcobalt silicided poly gate

A CoSi₂ salicidation process using a thin titanium capping layer is developed to improve the thermal stability of deep submicron CoSi₂/poly stacks. 50 nm CoSi₂ was uniformly formed on 0.25-μm wide poly lines. The electrical results show that the lines formed by a capping process using Ti can withstand higher thermal treatment (750° C for 30 min) without significant degradation. This work shows that the modified CoSi₂ process should be considered for 0.25-μm CMOS applications     

Technology limitations for N+/P+ polycidegate CMOS due to lateral dopant diffusion in silicide/polysilicon layers

The device degradation of dual-polycide-gate N⁺/P⁺ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NMOS:PMOS gate area ratios and thermal processing conditions. The simulations show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide technologies using low-temperature or short higher-temperature furnace steps. Simulations show that CoSi₂ and TiSi₂ appear to be better candidates for submicrometer dual-gate applications than WSi₂     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

The leakage current improvement in an ultrashallow junction NMOSwith Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 Å have been studied. In order to minimize the junction leakage current, the thickness of the CoSi₂ layer should he controlled under 300 Å and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi₂ layer into the channel direction when the gate spacer length was larger than 400 Å     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface