一种折叠内插式高速模数转换器的设计

描述了一种8bit,125MS/s采样率的折叠内插式ADC采用折叠内插结构设计。系统采用全并行结构的粗量化器实现高3位的量化编码,细量化部分采用折叠内插结构实现低5位的量化编码。电路设计中涉及分布式采样保持电路、折叠内插电路并在文章最后提出一种粗量化修正电路设计。通过HSPICE仿真测试,在采样频率为125MHz下对100M以内的输入频率测试,ADC信噪比达到40.0dB以上,功耗仅为170mW。     

Optical A/D Quantizer Scheme Based on Parallel Phase Modulators

A high-speed and high-resolution optical A/D quantizer is proposed. Its architecture is discussed. Bit circuits are built by using the phase modulators in parallel. Based on the different character of the half-wave voltage for every phase modulator and the polarized bias design of incident light, the RF input signal is coded and transmitted in the form of optical digital signal. According to the principle of the architecture, the high-resolution quantizers with 8-bit and 12-bit, et al. are built, which operate at 100 GS/s.Their quantization noise is invariable almost with bit circuits increasing. The simulation result of 4-bit A/D quantizer is also given.     

Indexing the output points of an LBVQ used for image transformcoding

A new method for indexing the points of a lattice-based vector quantizer (LBVQ) used to quantize the DCT coefficients of images is presented. With this method, a large number of lattice points can be selected as codewords. As a result, the quality of the compressed data can be very high. The problem is that the large number of points results in a high bit rate. To reduce the bit rate, a shorter representation is assigned to the more frequently used lattice points. These points are grouped and a prefix code is used to index these lattice points. Our method outperforms JPEG, particularly, in the case of images with high frequency components.     

A Power Optimized Continuous-Time ∆Σ ADC for Audio Applications

We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.     

Multiple frequencies and AR parameters estimation from one bitquantized signal via the EM algorithm

The authors present a novel algorithm which is used to estimate the coefficients of q AR processes from a coarsely quantized signal. The input signal to the quantizer is the superposition of q AR processes and noise. In a related problem a modified version of the above algorithm is used to estimate the frequencies of coarsely quantized data obtained from q sinusoids embedded in noise. The proposed algorithm can accommodate a nonuniform m-level quantizer, as well as the special case of a one bit quantizer. The proposed estimator is based on the maximum likelihood (ML) criterion, and is realized by judiciously combining the expectation-maximization (EM) algorithm of Dempster, Laird and Rubin (1977), and the “Gaussian fit” scheme of Curry (1970). Simulations reveal that they can accurately estimate the coefficients of several AR processes, or the frequencies of several sinusoids, from one bit quantized data at low signal to noise ratios and moderate number of observations     

A Flexible Architecture for Precise Gamma Correction

We present a flexible hardware architecture for precise gamma correction via piece-wise linear polynomial approximations. Arbitrary gamma values, input bit widths, and output bit widths are supported. The gamma correction curve is segmented via a combination of uniform segments and segments whose sizes vary by powers of two. This segmentation method minimizes the number of segments required, while providing an efficient way for indexing the polynomial coefficients. The outputs are guaranteed to be accurate to one unit in the last place through an analytical bit-width analysis methodology. Hardware realizations of various gamma correction designs are demonstrated on a Xilinx Virtex-4 field-programmable gate array (FPGA). A pipelined 12-bit input/8-bit output design on an XC4VLX100-12 FPGA occupies 146 slices and one digital signal processing slice. It is capable of performing 378 million gamma correction operations per second     

The design of high-order bandpass sigma-delta modulators using low-spread single-stage structure

A structure for single-stage high-order bandpass sigma-delta modulators (BPSDMs) is presented. The proposed structure introduces an additional internal path in each resonator, thus, adding one degree of freedom in coefficient determination. Coefficient spread can therefore be reduced, resulting in significantly reduced capacitance area in switched-capacitor BPSDM circuits. High-order BPSDMs with different quality factors (Q) are demonstrated. It shows that coefficient spread is significantly reduced, especially for high-Q applications. For comparable eighth-order 3-bit BPSDMs, the maximum coefficient spread are respectively 15369 and 7693 for conventional cascade-of-resonator-with-feedback (CRFB) and cascade-of-resonator-with-feedforward (CRFF) designs, and 114 for the proposed structure. For an eighth-order 1-bit example, these respective values are 8994, 2638, and 74. With coefficient mismatch, peak signal-to-noise ratio (PSNR) degradation of the proposed structure is less than those of the CRFB and CRFF structures, demonstrating reduced sensitivity to component mismatch. Hence, the proposed structure can reduce chip area and ease circuit implementation of BPSDMs.     

Optimal differential energy watermarking of DCT encoded images andvideo

This paper proposes the differential energy watermarking (DEW) algorithm for JPEG/MPEG streams. The DEW algorithm embeds label bits by selectively discarding high frequency discrete cosine transform (DCT) coefficients in certain image regions. The performance of the proposed watermarking algorithm is evaluated by the robustness of the watermark, the size of the watermark, and the visual degradation the watermark introduces. These performance factors are controlled by three parameters, namely the maximal coarseness of the quantizer used in pre-encoding, the number of DCT blocks used to embed a single watermark bit, and the lowest DCT coefficient that we permit to be discarded. We follow a rigorous approach to optimizing the performance and choosing the correct parameter settings by developing a statistical model for the watermarking algorithm. Using this model, we can derive the probability that a label bit cannot be embedded. The resulting model can be used, for instance, for maximizing the robustness against re-encoding and for selecting adequate error correcting codes for the label bit string.     

一种基于小波变换的高倍数SAR原始数据压缩算法

该文提出了一种基于分块提升小波变换的SAR原始数据压缩算法。在该算法中,针对SAR原始数据特点,提出一种有效的小波子带比特分配策略,为获得最优量化增益,在高比特率和低比特率两种情况下,分别采用均匀和非均匀Lloyd-Max量化器对小波系数进行量化。实验结果表明,该算法与传统BAQ和BAVQ算法相比,在信噪比和图像质量等各方面指标都取得了明显的改善。     

An efficient two-digit adaptive delta modulation for Laplacian source coding

Delta Modulation (DM) is a simple waveform coding algorithm used mostly when timely data delivery is more important than the transmitted data quality. While the implementation of DM is fairly simple and inexpensive, it suffers from several limitations, such as slope overload and granular noise, which can be overcome using Adaptive Delta Modulation (ADM). This paper presents novel 2-digit ADM with six-level quantization using variable-length coding, for encoding the time-varying signals modelled by Laplacian distribution. Two variants of quantizer are employed, distortion-constrained quantizer which is optimally designed for minimal mean-squared error (MSE), and rate-constrained quantizer, which is suboptimal in the minimal MSE sense, but enables minimal loss in SQNR for the target bit rate. Experimental results using real speech signal are provided, indicating that the proposed configuration outperforms the baseline ADM algorithms, including Constant Factor Delta Modulation (CFDM), Continuously Variable Slope Delta Modulation (CVSDM), 2-digit and 2-bit ADM, and operates in a much wider dynamic range.     

Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator

A detailed analysis of the impact of a hysteretic quantizer on a multibit, Sigma-Delta modulator has been carried out in this paper. Both discrete-time and continuous-time modulators have been considered. A qualitative modeling of the hysteretic quantizer based on a hysteretic block followed by an ideal quantizer was proposed. Due to the hysteresis effect, the quantizer output signal is delayed and distorted with respect to the quantizer input signal, where the delay causes a phase-shift independent on the signal frequency. Yet, the effect of the hysteresis depends on the input signal amplitude. This model was validated by using system-level simulations for a second order, 3-bit, discrete-time Sigma-Delta modulator. A linear model for hysteresis was derived by assuming a narrow hysteresis cycle. The quantizer input signal plays a fundamental role in the discussion. In order to include this signal into the linear analysis some approximations are proposed. The quantizer output signal is decomposed by the use of the Fourier series analysis only into the in-phase and quadrature components (with respect to the input signal) whose Fourier series coefficients can be analytically calculated. A quantitative analysis for both a second order, 3-bit, DT and CT Sigma-Delta modulators including a hysteretic quantizer was carried out. For the CT modulator, finite GBW in amplifiers, excess loop delay, and a hysteretic quantizer were considered separately and combined. A good agreement with both system-level simulations and experimental results is found, despite the approximations considered for the quantizer input signal.     

Design of Semi-Uniform Quantizers and Their Application in Sigma Delta A/D Converters

In this paper a new type of non-uniform quantizer, semi-uniform quantizer, is introduced. A k-bit semi-uniform quantizer uses the thresholds defined by a (k + 1)-bit uniform quantizer and arranges them in such a way that small-amplitude inputs will be quantized by small quantization steps and large-amplitude inputs by large quantization steps. Therefore the total quantization error power could be reduced and the modulator's dynamic range could be increased by 1-bit. The condition for a semi-uniform quantizer to achieve a better performance than a uniform quantizer is analyzed and verified using a second order 3-bit sigma delta modulator prototype chip, fabricated in 0.35 μm CMOS process. At 32× oversampling ratio the modulator achieves 81 dB dynamic range and 63.8 dB peak SNDR with 3-bit semi-uniform quantizer. With 3-bit uniform quantizer the dynamic range is 70 dB and the peak SNDR is 54.1 dB.     

Block transform image coding by multistage vector quantization withoptimal bit allocation

A multistage vector quantization with optimal bit allocation (MVQ-OBA) in the transform domain is presented. A set of bit allocation planes is first obtained by slicing a (scalar) optimal bit allocation map where the number of bits assigned to each coefficient is proportional to the coefficient variance. The set of bit allocation planes determines the coefficients to be used and the codebook size at each stage. The vector dimensionalities are restricted to small values and relatively small codebooks are used, thus reducing both the overhead required for transmitting the codebooks and the complexity in codebook design. The computer simulation results demonstrate that MVQ-OBA is competitive with many other transform coding techniques including variable length transform coding. MVQ-OBA is well suited for progressive transmission     

Optimum design of vector-quantized subband codecs

This article provides an approach for representing an optimum vector quantizer by a scalar nonlinear gain-plus-additive noise model. The validity and accuracy of this analytic model is confirmed by comparing the calculated model quantization errors with actual simulation of the optimum Linde-Buzo-Gray (1980) vector quantizer. Using this model, we form an MSE measure of an M-band filter bank codec in terms of the equivalent scalar quantization model and find the optimum FIR filter coefficients for each channel in the M-band structure for a given bit rate, filter length, and input signal correlation model. Specific design examples are worked out for four-tap filters in the two-band paraunitary case. These theoretical results are confirmed by extensive Monte Carlo simulation     

Smooth side-match classified vector quantizer with variable blocksize

Although the side-match vector quantizer (SMVQ) reduces the bit rate, the image coding quality by SMVQ generally degenerates as the gray level transition across the boundaries of the neighboring blocks is increasing or decreasing. This study presents a smooth side-match method to select a state codebook according to the smoothness of the gray levels between neighboring blocks. This method achieves a higher PSNR and better visual perception than SMVQ does for the same bit rate. Moreover, to design codebooks, a genetic clustering algorithm that automatically finds the appropriate number of clusters is proposed. The proposed smooth side-match classified vector quantizer (SSM-CVQ) is thus a combination of three techniques: the classified vector quantization, the variable block size segmentation and the smooth side-match method. Experimental results indicate that SSM-CVQ has a higher PSNR and a lower bit rate than other methods. Furthermore, the Lena image can be coded by SSM-CVQ with 0.172 bpp and 32.49 dB in PSNR.     

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulatorin CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators-referred to as a 2-1-1_mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2.1.1_single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four     

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.     

Transform and Hybrid Transform/DPCM Coding of Images Using Pyramid Vector Quantization

The transform and hybrid transform/DPCM methods of image coding are generalized to allow pyramid vector quantization of the transform coefficients. An asymptotic mean-squared error performance expression is derived for the pyramid vector quantizer and used to determine the optimum rate assignment for encoding the various transform coefficients. Coding simulations for two images at average rates of 0.5-1 bit/pixel demonstrate a 1-3 dB improvement in signal-to-noise ratio for the vector quantization approach in the hybrid coding, with more modest improvements in signal-to-noise ratio in the transform coding. However, this improvement is quite noticeable in image quality, particularly in reducing "blockiness" in the low bit rate encoded images.     

基于最佳量化的序列图像编码转换码率控制策略

该文分析了编码转换缓冲区的状态,导出了编码转换缓冲区为防止解码器缓冲区下溢和上溢应满足的条件,建立了序列图像编码转换模型。并根据编码转换缓冲器的状态和信道速率,为待编码帧在图像层上预分配目的序列图像编码比特数,使用DCT系数分布特性来表征图像特性。继而为帧内每一具体宏块选定最佳量化因子,提出了基于最佳量化的码率控制策略,模拟实验表明,该码率控制策略能有效地减少、避免缓冲区出现上、下溢的情况,使输出码率趋于稳定,提高了重建序列图像的信噪比。     

Subjective Evaluation of an Adaptive Differential Voice Encoder with Oversampling and Entropy Coding

An adaptive differential speech encoder was assessed using subjective evaluation procedures. The coder's adaptive quantizer was similar to the one used by Cohn and Melsa [1] and the predictor involved nonadaptive previous-sample feedback. The digital channel used to transmit the quantizer output levels was assumed error-free. Paired comparison tests were used to obtain scaled isopreference contours on theN-fplane, whereNandfdenote, respectively, the number of quantizer output levels and the sampling rate relative to the Nyquist rate. These contours were used to determine the subjective signal-to-noise ratio vs.fandN, maximum subjective signal-signal-to-noise ratios vs. bit rate, optimum values offandN, and bit-rate savings which occur when entropy coding is used instead of natural coding of the quantizer output levels. Entropy coding yielded a bit rate approximately equal to threequarters that for natural coding and Nyquist-rate sampling minimized the bit rate in each case. Savings of from one to two bits occurred when ADPCM was compared with nonadaptive DPCM. The fact that our system was better than others forf simeq 1.0but worse forf gsim 2.0indicates the need to modify our quantizer adaptation algorithm as the sampling rate increases relative to the Nyqusit rate.